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An O(n) algorithm for transistor stacking with performance constraints

Authors:

Bulent Basaran,

Rob A. RutenbarAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 221 - 226

https://doi.org/10.1145/240518.240559

Published: 01 June 1996 Publication History

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Sorokin ARyzhenko NHomayoun HTaskin BMohsenin TZhao W(2019)SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean RoutingProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317965(159-164)Online publication date: 13-May-2019
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Babu AAnand B(2019)Modified Dynamic Current mode logic based LFSR for low power applicationsMicroprocessors and Microsystems10.1016/j.micpro.2019.102945(102945)Online publication date: Nov-2019
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Cremer PHougardy SSchneider JSilvanus JOzdal MChu C(2017)Automatic Cell Layout in the 7nm EraProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036672(99-106)Online publication date: 19-Mar-2017
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Index Terms

An O(n) algorithm for transistor stacking with performance constraints
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
2. Theory of computation
  1. Computational complexity and cryptography
    1. Complexity classes

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Sorokin ARyzhenko NHomayoun HTaskin BMohsenin TZhao W(2019)SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean RoutingProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317965(159-164)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3317965
Babu AAnand B(2019)Modified Dynamic Current mode logic based LFSR for low power applicationsMicroprocessors and Microsystems10.1016/j.micpro.2019.102945(102945)Online publication date: Nov-2019
https://doi.org/10.1016/j.micpro.2019.102945
Cremer PHougardy SSchneider JSilvanus JOzdal MChu C(2017)Automatic Cell Layout in the 7nm EraProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036672(99-106)Online publication date: 19-Mar-2017
https://dl.acm.org/doi/10.1145/3036669.3036672
Chen GFujimura TDong QNakatake SYang B(2016)DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog LayoutACM Transactions on Design Automation of Electronic Systems10.1145/288839521:3(1-21)Online publication date: 11-May-2016
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Hougardy SNieberg TSchneider J(2013)BonnCell: Automatic layout of leaf cells2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509638(453-460)Online publication date: Jan-2013
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Yan TNakatake SNojima T(2006)Formulating the Empirical Strategies in Module Generation of Analog MOS LayoutProceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures10.1109/ISVLSI.2006.47Online publication date: 2-Mar-2006
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Hartono RJangkrajarng NBhattacharya SShi C(2005)Automatic Device Layout Generation for Analog Layout RetargetingProceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design10.1109/ICVD.2005.60(457-462)Online publication date: 3-Jan-2005
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Di Long Yijie Zeng Changxu Du Xianlong Hong Sheqin Dong (2004)A novel performance-driven automatic layout tool for analog circuit2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914)10.1109/ICCCAS.2004.1346420(1344-1348)Online publication date: 2004
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Gielen GRutenbar R(2001)Synthesis of analog and mixed-signal integrated electronic circuitsFormal engineering design synthesis10.5555/762002.762016(391-427)Online publication date: 1-Jan-2001
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Gate leakage reduction for scaled devices using transistor stacking

Improving the subthreshold performance of junctionless transistor using spacer engineering

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Gate leakage reduction for scaled devices using transistor stacking

Improving the subthreshold performance of junctionless transistor using spacer engineering

Impact of high-k spacer on device performance of a junctionless transistor

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