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Glitch analysis and reduction in register transfer level power optimization

Authors:

Anand Raghunathan,

Sujit Dey,

Niraj K. JhaAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 331 - 336

https://doi.org/10.1145/240518.240581

Published: 01 June 1996 Publication History

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References

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Cited By

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Wong JCheung P(2013)Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition ProbabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.223028021:12(2307-2320)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2230280
Raffelsieper MMousavi M(2011)Symbolic power analysis of cell librariesProceedings of the 16th international conference on Formal methods for industrial critical systems10.5555/2037070.2037081(134-148)Online publication date: 29-Aug-2011
https://dl.acm.org/doi/10.5555/2037070.2037081
Yang BKarri REles PJantsch ABergamaschi R(2005)Power optimization for universal hash function data path using divide-and-concatenate techniqueProceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1084834.1084891(219-224)Online publication date: 19-Sep-2005
https://dl.acm.org/doi/10.1145/1084834.1084891
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Index Terms

Glitch analysis and reduction in register transfer level power optimization
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
    2. Logic synthesis
      1. Circuit optimization

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DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Wong JCheung P(2013)Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition ProbabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.223028021:12(2307-2320)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2230280
Raffelsieper MMousavi M(2011)Symbolic power analysis of cell librariesProceedings of the 16th international conference on Formal methods for industrial critical systems10.5555/2037070.2037081(134-148)Online publication date: 29-Aug-2011
https://dl.acm.org/doi/10.5555/2037070.2037081
Yang BKarri REles PJantsch ABergamaschi R(2005)Power optimization for universal hash function data path using divide-and-concatenate techniqueProceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1084834.1084891(219-224)Online publication date: 19-Sep-2005
https://dl.acm.org/doi/10.1145/1084834.1084891
Givargis TVahid FHenkel JYoshida K(2000)A hybrid approach for core-based system-level power modelingProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368593(141-146)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368593
Benini LDe Micheli GMacii AMacii EPoncino MScarsi R(1999)Glitch power minimization by gate freezingProceedings of the conference on Design, automation and test in Europe10.1145/307418.307481(36-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307481
Khouri KLakshminarayana GJha NDewilde PRammig FMusgrave G(1998)IMPACTProceedings of the conference on Design, automation and test in Europe10.5555/368058.368436(848-854)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368436
Lakshminarayana GRaghunathan AJha NDey SYasuura H(1998)Transforming control-flow intensive designs to facilitate power managementProceedings of the 1998 IEEE/ACM international conference on Computer-aided design10.1145/288548.289107(657-664)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.1145/288548.289107
Benini LHodgson RSiegel PChandrakasan AKiaei S(1998)System-level power estimation and optimizationProceedings of the 1998 international symposium on Low power electronics and design10.1145/280756.280881(173-178)Online publication date: 10-Aug-1998
https://dl.acm.org/doi/10.1145/280756.280881
Seko TNakamura AKikuno T(1998)Measurement of glitches based on variable gate delay model using VHDL simulatorIEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242)10.1109/APCCAS.1998.743934(767-770)Online publication date: 1998
https://doi.org/10.1109/APCCAS.1998.743934
Raghunathan ADey SJha NWakabayashi KYoffa EDe Micheli GRabaey J(1997)Power management techniques for control-flow intensive designsProceedings of the 34th annual Design Automation Conference10.1145/266021.266191(429-434)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266191
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A 9-bit 80 MS/s successive approximation register analog-to-digital converter with a capacitor reduction technique

Glitch-free NAND-based digitally controlled delay-lines

Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP

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A 9-bit 80 MS/s successive approximation register analog-to-digital converter with a capacitor reduction technique

Glitch-free NAND-based digitally controlled delay-lines

Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP

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