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Constructing lower and upper bounded delay routing trees using linear programming

Authors:

Jaewon Oh,

Iksoo Pyo,

Massoud PedramAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 401 - 404

https://doi.org/10.1145/240518.240595

Published: 01 June 1996 Publication History

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References

[1]

M. A. B. Jackson, A. Srinivasan, and E. S. Kuh, "Clock routing for high-performance ICs," 27th Design Automation Conference, pp. 573-579, 1990.

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R-S Tsay, "Exact zero skew," International Conference on Computer-Aided Design, pp. 336-339, 1991.

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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE International Conference on ASIC, pp. 1.1.1-1.1.5, 1992.

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J. Cong and C-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," International Symposium on Circuits and Systems, pp. 215-218, 1995.

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D. J.-H. Huang, A. B. Kahng and C-W. Tsao, "On the Bounded-Skew Clock and Steiner Routing Problems," 32nd Design Automation Conference, pp. 508-513, 1995.

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J. Xi, W-M. Dai, "Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution," 32nd Design Automation Conference, pp. 491-496, 1995

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R. J. Vanderbei, "LOQO User's Manual," Program and the manual are available free for academic users at ftp://elib.zibberlin.de/pub/opt-net/software/loqo.

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J. Oh, I. Pyo and M. Pedram, "Contructing Lower and Upper Bounded Delay Routing Trees Using Linear Programmin," USC Electrical Engineering Department - Systems, Technical Report 96-05, Mar. 1996.

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Cited By

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Fatemi HKahng AKim Mde Gyvez JKahng A(2020)Optimal bounded-skew steiner trees to minimize maximum k-active dynamic powerProceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop10.1145/3414622.3431908(1-8)Online publication date: 5-Nov-2020
https://dl.acm.org/doi/10.1145/3414622.3431908
Han KKahng AMoyes CZelikovsky AHu S(2018)A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructionsProceedings of the 20th System Level Interconnect Prediction Workshop10.1145/3225209.3225215(1-8)Online publication date: 23-Jun-2018
https://dl.acm.org/doi/10.1145/3225209.3225215
Chan THan KKahng ALee JNath SCavallaro JZhang TJones ALi H(2014)OCV-aware top-level clock tree optimizationProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591541(33-38)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591541
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Index Terms

Constructing lower and upper bounded delay routing trees using linear programming
1. Mathematics of computing
  1. Mathematical analysis
    1. Mathematical optimization
      1. Continuous optimization
        Linear programming
2. Theory of computation
  1. Design and analysis of algorithms
    1. Mathematical optimization
      1. Continuous optimization
        Linear programming

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Fatemi HKahng AKim Mde Gyvez JKahng A(2020)Optimal bounded-skew steiner trees to minimize maximum k-active dynamic powerProceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop10.1145/3414622.3431908(1-8)Online publication date: 5-Nov-2020
https://dl.acm.org/doi/10.1145/3414622.3431908
Han KKahng AMoyes CZelikovsky AHu S(2018)A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructionsProceedings of the 20th System Level Interconnect Prediction Workshop10.1145/3225209.3225215(1-8)Online publication date: 23-Jun-2018
https://dl.acm.org/doi/10.1145/3225209.3225215
Chan THan KKahng ALee JNath SCavallaro JZhang TJones ALi H(2014)OCV-aware top-level clock tree optimizationProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591541(33-38)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591541
Liu IChou TAziz AWong DWiesel MHill D(2000)Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertionProceedings of the 2000 international symposium on Physical design10.1145/332357.332370(33-38)Online publication date: 1-May-2000
https://dl.acm.org/doi/10.1145/332357.332370
Cho JSarrafzadeh M(1999)Vlsi Circuit LayoutWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W1801Online publication date: 27-Dec-1999
https://doi.org/10.1002/047134608X.W1801
Pedram MVaishnav H(1997)Power Optimization in VLSI LayoutJournal of VLSI Signal Processing Systems10.5555/257692.281303715:3(221-232)Online publication date: 1-Mar-1997
https://dl.acm.org/doi/10.5555/257692.2813037
Wei Huang Kahng A(1997)A layout advisor for timing-critical bus routingProceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)10.1109/ASIC.1997.617007(210-214)Online publication date: 1997
https://doi.org/10.1109/ASIC.1997.617007
Cong JHe LKoh C(1997)Layout OptimizationLow Power Design in Deep Submicron Electronics10.1007/978-1-4615-5685-5_8(205-265)Online publication date: 1997
https://doi.org/10.1007/978-1-4615-5685-5_8

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Constructing minimal spanning/Steiner trees with bounded path length

Upper and Lower Bounds on Constructing Alphabetic Binary Trees

Constructing Minimal Spanning/Steiner Trees with Bounded Path Length

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