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Power estimation of cell-based CMOS circuits

Authors:

Alessandro Bogiolo,

Luca Benini,

Bruno RiccòAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 433 - 438

https://doi.org/10.1145/240518.240601

Published: 01 June 1996 Publication History

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Cited By

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Joseph ARachamalla SRao RHaridass ANalla P(2016)FVCAGProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934633(260-265)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934633
Raffelsieper MMousavi M(2011)Symbolic power analysis of cell librariesProceedings of the 16th international conference on Formal methods for industrial critical systems10.5555/2037070.2037081(134-148)Online publication date: 29-Aug-2011
https://dl.acm.org/doi/10.5555/2037070.2037081
Kim KKim THwang TKang SLiu C(2002)Logic transformation for low-power synthesisACM Transactions on Design Automation of Electronic Systems10.1145/544536.5445397:2(265-283)Online publication date: 1-Apr-2002
https://dl.acm.org/doi/10.1145/544536.544539
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Index Terms

Power estimation of cell-based CMOS circuits
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrough effect. Based on the model, a Cell-Based Power Estimation (CBPE) method ...

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DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

Acceptance Rates

DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Joseph ARachamalla SRao RHaridass ANalla P(2016)FVCAGProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934633(260-265)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934633
Raffelsieper MMousavi M(2011)Symbolic power analysis of cell librariesProceedings of the 16th international conference on Formal methods for industrial critical systems10.5555/2037070.2037081(134-148)Online publication date: 29-Aug-2011
https://dl.acm.org/doi/10.5555/2037070.2037081
Kim KKim THwang TKang SLiu C(2002)Logic transformation for low-power synthesisACM Transactions on Design Automation of Electronic Systems10.1145/544536.5445397:2(265-283)Online publication date: 1-Apr-2002
https://dl.acm.org/doi/10.1145/544536.544539
Zheng LTenhunen H(2002)Design and Analysis of Power Integrity in Deep Submicron System-on-Chip CircuitsAnalog Integrated Circuits and Signal Processing10.1023/A:101244461930730:1(15-29)Online publication date: 10-Jan-2002
https://dl.acm.org/doi/10.1023/A%3A1012444619307
Bogliolo ABenini LDe Micheli G(2000)Regression-based RTL power modelingACM Transactions on Design Automation of Electronic Systems10.1145/348019.3480815:3(337-372)Online publication date: Jul-2000
https://doi.org/10.1145/348019.348081
Benini LDe Micheli G(2000)Synthesis of low-power selectively-clocked systems from high-level specificationACM Transactions on Design Automation of Electronic Systems10.1145/348019.3480505:3(311-321)Online publication date: Jul-2000
https://doi.org/10.1145/348019.348050
Bogliolo ABenini LRiccó BDe Micheli GNajim FCong JBlaauw D(1999)Efficient switching activity computation during high-level synthesis of control-dominated designsProceedings of the 1999 international symposium on Low power electronics and design10.1145/313817.313896(127-132)Online publication date: 17-Aug-1999
https://dl.acm.org/doi/10.1145/313817.313896
Bogliolo ABenini LDe Micheli G(1997)Adaptive least mean square behavioral power modelingProceedings of the 1997 European conference on Design and Test10.5555/787260.787698Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787698
Benini LVuillod PBogliolo ADe Micheli G(1997)Clock Skew Optimization for Peak Current ReductionHigh Performance Clock Distribution Networks10.1007/978-1-4684-8440-3_2(5-18)Online publication date: 1997
https://doi.org/10.1007/978-1-4684-8440-3_2
Benini LVuillod Pde Micheli GCoelho C(1996)Synthesis of low-power selectively-clocked systems from high-level specificationProceedings of the 9th international symposium on System synthesis10.5555/524431.857927Online publication date: 6-Nov-1996
https://dl.acm.org/doi/10.5555/524431.857927
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Quaternary CMOS Combinational Logic Circuits

Synthesis of High Performance Low Power Dynamic CMOS Circuits

A cell-based power estimation in CMOS combinational circuits

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Quaternary CMOS Combinational Logic Circuits

Synthesis of High Performance Low Power Dynamic CMOS Circuits

A cell-based power estimation in CMOS combinational circuits

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