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Address calculation for retargetable compilation and exploration of instruction-set architectures

Authors:

Clifford Liem,

Pierre Paulin,

Ahmed JerrayaAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 597 - 600

https://doi.org/10.1145/240518.240631

Published: 01 June 1996 Publication History

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Cited By

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Llopard ICohen AFabre CMartin JCharles HBernard CBrandner FAa T(2013)Code generation for an application-specific VLIW processor with clustered, addressable register filesProceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems10.1145/2443608.2443612(11-19)Online publication date: 24-Feb-2013
https://dl.acm.org/doi/10.1145/2443608.2443612
Taniguchi ITalavera GCatthoor F(2012)Energy-Efficient Address-Generation Units and Their Design MethodologyEnergy-Aware Memory Management for Embedded Multimedia Systems10.1201/b11418-11(309-341)Online publication date: 4-Jan-2012
https://doi.org/10.1201/b11418-11
Lokuciejewski PMarwedel PLokuciejewski PMarwedel P(2011)WCET-Aware Source Code Level OptimizationsWorst-Case Execution Time Aware Compilation Techniques for Real-Time Systems10.1007/978-90-481-9929-7_4(61-129)Online publication date: 2011
https://doi.org/10.1007/978-90-481-9929-7_4
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Index Terms

Address calculation for retargetable compilation and exploration of instruction-set architectures
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

Acceptance Rates

DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Llopard ICohen AFabre CMartin JCharles HBernard CBrandner FAa T(2013)Code generation for an application-specific VLIW processor with clustered, addressable register filesProceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems10.1145/2443608.2443612(11-19)Online publication date: 24-Feb-2013
https://dl.acm.org/doi/10.1145/2443608.2443612
Taniguchi ITalavera GCatthoor F(2012)Energy-Efficient Address-Generation Units and Their Design MethodologyEnergy-Aware Memory Management for Embedded Multimedia Systems10.1201/b11418-11(309-341)Online publication date: 4-Jan-2012
https://doi.org/10.1201/b11418-11
Lokuciejewski PMarwedel PLokuciejewski PMarwedel P(2011)WCET-Aware Source Code Level OptimizationsWorst-Case Execution Time Aware Compilation Techniques for Real-Time Systems10.1007/978-90-481-9929-7_4(61-129)Online publication date: 2011
https://doi.org/10.1007/978-90-481-9929-7_4
Rajagopalan SMalik S(2010)Retargetable Very Long InstructionWord Compiler Framework for Digital Signal ProcessorsThe Compiler Design Handbook10.1201/9781420040579.ch16Online publication date: 7-Mar-2010
https://doi.org/10.1201/9781420040579.ch16
Taniguchi IJayapala MRaghavan PCatthoor FSakanushi KTakeuchi YImai MWakabayashi K(2009)Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processorsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509742(449-454)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509742
TANIGUCHI IRAGHAVAN PJAYAPALA MCATTHOOR FTAKEUCHI YIMAI M(2009)Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded ProcessorsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.1161E92-A:4(1161-1173)Online publication date: 2009
https://doi.org/10.1587/transfun.E92.A.1161
Taniguchi IJayapala MRaghavan PCatthoor FSakanushi KTakeuchi YImai M(2009)Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors2009 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2009.4796521(449-454)Online publication date: Jan-2009
https://doi.org/10.1109/ASPDAC.2009.4796521
Talavera GJayapala MCarrabina JCatthoor F(2008)Address Generation Optimization for Embedded High-Performance ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0165-y53:3(271-284)Online publication date: 1-Dec-2008
https://dl.acm.org/doi/10.1007/s11265-008-0165-y
Ozturk OKandemir MTosun SQu GIsmail YNarayanan VZhou H(2006)An ILP based approach to address code generation for digital signal processorsProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127919(37-42)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127919
Gebotys C(2006)A minimum-cost circulation approach to DSP address-code generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.76672418:6(726-741)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.766724
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Increasing the instruction fetch rate via block-structured instruction set architectures

Block enlargement optimizations for increasing the instruction fetch rate in block-structured instruction set architectures

Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures

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Increasing the instruction fetch rate via block-structured instruction set architectures

Block enlargement optimizations for increasing the instruction fetch rate in block-structured instruction set architectures

Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures

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