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Reducing power dissipation after technology mapping by structural transformations

Authors:

Bernhard Rohfleisch,

Alfred Kölbl,

Bernd WurthAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 789 - 794

https://doi.org/10.1145/240518.240667

Published: 01 June 1996 Publication History

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Cited By

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Alves NNepal KDworak JBahar RBenini LDe Micheli GAl-Hashimi BMueller W(2009)Detecting errors using multi-cycle invariance informationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874815(791-796)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874815
Alves NNepal KDworak JBahar R(2009)Detecting errors using multi-cycle invariance information2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090771(791-796)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090771
Son YNa J(2004)A New Logic Transformation Method for Both Low Power and High TestabilityIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-30205-6_79(770-779)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30205-6_79
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Index Terms

Reducing power dissipation after technology mapping by structural transformations
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Alves NNepal KDworak JBahar RBenini LDe Micheli GAl-Hashimi BMueller W(2009)Detecting errors using multi-cycle invariance informationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874815(791-796)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874815
Alves NNepal KDworak JBahar R(2009)Detecting errors using multi-cycle invariance information2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090771(791-796)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090771
Son YNa J(2004)A New Logic Transformation Method for Both Low Power and High TestabilityIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-30205-6_79(770-779)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30205-6_79
Son YChong J(2003)A New Logic Design Method for Considering Low Power and High TestabilitySystem-on-Chip for Real-Time Applications10.1007/978-1-4615-0351-4_30(327-338)Online publication date: 2003
https://doi.org/10.1007/978-1-4615-0351-4_30
Muroyama MHyodo AYasuura HIshihara T(2002)A Power Minimization Technique for Arithmetic Circuits by Cell SelectionProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835376Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835376
Kim KKim THwang TKang SLiu C(2002)Logic transformation for low-power synthesisACM Transactions on Design Automation of Electronic Systems10.1145/544536.5445397:2(265-283)Online publication date: 1-Apr-2002
https://dl.acm.org/doi/10.1145/544536.544539
Benini LMicheli G(2002)Logic Synthesis for Low PowerLogic Synthesis and Verification10.1007/978-1-4615-0817-5_8(197-223)Online publication date: 2002
https://doi.org/10.1007/978-1-4615-0817-5_8
Chang CHu BMarek-Sadowska M(2001)In-place delay constrained power optimization using functional symmetriesProceedings of the conference on Design, automation and test in Europe10.5555/367072.367275(377-382)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367275
Veneris AAbadir MTing IGoto S(2001)Design rewiring based on diagnosis techniquesProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370516(479-484)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370516
Sundararajan VParhi K(1999)Low Power Gate Resizing of Combinational Circuits by Buffer-RedistributionProceedings of the 20th Anniversary Conference on Advanced Research in VLSI10.5555/786453.786725Online publication date: 21-Mar-1999
https://dl.acm.org/doi/10.5555/786453.786725
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Short-circuit power driven gate sizing technique for reducing power dissipation

Low-power technology mapping for FPGA architectures with dual supply voltages

Power dissipation impact of the technology mapping synthesis on look-up table architectures

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Short-circuit power driven gate sizing technique for reducing power dissipation

Low-power technology mapping for FPGA architectures with dual supply voltages

Power dissipation impact of the technology mapping synthesis on look-up table architectures

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