research-article

A counterexample-guided interpolant generation algorithm for SAT-based model checking

Authors:

Chung-Yang (Ric) HuangAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 118, Pages 1 - 6

https://doi.org/10.1145/2463209.2488879

Published: 29 May 2013 Publication History

Abstract

Interpolation is an important and distinguished method popularly applied to recent synthesis and verification research topics. Existing approaches generate interpolants by analysing unsatisfiability proofs from SAT solvers. Unfortunately, the interpolant is predestinedly determined by how the unsatisfiability proof is logged. This particularly weakens the abstraction of interpolation-based model checking procedure. In this paper, a new approach to generate a variety of functionally different interpolants using simulation and SAT solving is proposed. We further seamlessly integrated the novel interpolant generation algorithm into the reinterpreted interpolation-based model checking procedure. Moreover, spurious counterexamples from the model checker further guide the generation of interpolants to refute excessive refinements. As an extra benefit, proof logging is not required for SAT solvers. Experiments show promising results of our interpolation-based model checker NewITP on solving a large set of HWMCC benchmarks.

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Cited By

Ivrii AVizel Y(2024)Bit-Level Model CheckingHandbook of Computer Architecture10.1007/978-981-97-9314-3_35(1203-1242)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_35
Ivrii AVizel Y(2022)Bit-Level Model CheckingHandbook of Computer Architecture10.1007/978-981-15-6401-7_35-1(1-40)Online publication date: 13-Apr-2022
https://doi.org/10.1007/978-981-15-6401-7_35-1
Alouneh SAbed SAl Shayeji MMesleh R(2018)A comprehensive study and analysis on SAT-solvers: advances, usages and achievementsArtificial Intelligence Review10.1007/s10462-018-9628-0Online publication date: 28-Mar-2018
https://doi.org/10.1007/s10462-018-9628-0
Show More Cited By

Index Terms

A counterexample-guided interpolant generation algorithm for SAT-based model checking
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Ivrii AVizel Y(2024)Bit-Level Model CheckingHandbook of Computer Architecture10.1007/978-981-97-9314-3_35(1203-1242)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_35
Ivrii AVizel Y(2022)Bit-Level Model CheckingHandbook of Computer Architecture10.1007/978-981-15-6401-7_35-1(1-40)Online publication date: 13-Apr-2022
https://doi.org/10.1007/978-981-15-6401-7_35-1
Alouneh SAbed SAl Shayeji MMesleh R(2018)A comprehensive study and analysis on SAT-solvers: advances, usages and achievementsArtificial Intelligence Review10.1007/s10462-018-9628-0Online publication date: 28-Mar-2018
https://doi.org/10.1007/s10462-018-9628-0
Lai CWu CHuang C(2014)Adaptive interpolation-based model checking2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2014.6742979(744-749)Online publication date: Jan-2014
https://doi.org/10.1109/ASPDAC.2014.6742979

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