research-article

Skew-bounded low swing clock tree optimization

Authors:

Can Sitik,

Baris TaskinAuthors Info & Claims

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Pages 49 - 54

https://doi.org/10.1145/2483028.2483059

Published: 02 May 2013 Publication History

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Abstract

This paper introduces a methodology that optimizes the performance of a low swing clock tree under a skew bound. Low-swing clock trees are preferred for a reduction in the clock switching power, with an expected trade-off in clock slew and skew. In this paper, a heuristic optimization process is introduced that keeps the clock skew under the same skew budget of the originating full-swing clock tree. In this low swing clock optimization, the low power consumption property is preserved. The effect of slew on the logic timing, which is naturally degraded due to low-swing operation, is analyzed within timing slack of some paths in order to highlight the effectiveness of the low swing clock trees in lowering power consumption with limited impact on timing constraints. The experiments performed with the 4 largest ISCAS'89 benchmark circuits operating at 500~MHz, 90~nm technology and 4 different V_dd levels show that the optimized low swing clock tree can achieve an average of upto 11.0% reduction in the power consumption with no more than a skew degradation of 0.5% of the clock period (i.e. within the practical skew budget).

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Cited By

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Sitik CLiu WTaskin BSalman EHomayoun HTaskin BMohsenin TZhao W(2019)Low Voltage Clock Tree Synthesis with Local Gate ClustersProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318004(99-104)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318004
Lerner STaskin B(2019)Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree SynthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.287457227:1(1-10)Online publication date: Jan-2019
https://doi.org/10.1109/TVLSI.2018.2874572
Sitik CLiu WTaskin BSalman E(2016)Design Methodology for Voltage-Scaled Clock Distribution NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253992624:10(3080-3093)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2539926
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Index Terms

Skew-bounded low swing clock tree optimization
1. Hardware
  1. Very large scale integration design

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Published In

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

May 2013

368 pages

ISBN:9781450320320

DOI:10.1145/2483028

General Chair:
Jose L. Ayala
Complutense University of Madrid, Spain
,
Program Chairs:
Alex Jones
University of Pittsburgh, USA
,
Patrick Madden
Binghamton University, USA
,
Publications Chair:
Ayse K. Coskun
Boston University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 May 2013

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GLSVLSI'13: Great Lakes Symposium on VLSI 2013

May 2 - 3, 2013

Paris, France

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GLSVLSI '13 Paper Acceptance Rate 76 of 238 submissions, 32%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all

Sitik CLiu WTaskin BSalman EHomayoun HTaskin BMohsenin TZhao W(2019)Low Voltage Clock Tree Synthesis with Local Gate ClustersProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318004(99-104)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318004
Lerner STaskin B(2019)Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree SynthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.287457227:1(1-10)Online publication date: Jan-2019
https://doi.org/10.1109/TVLSI.2018.2874572
Sitik CLiu WTaskin BSalman E(2016)Design Methodology for Voltage-Scaled Clock Distribution NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253992624:10(3080-3093)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2539926
Sitik CSalman EFilippini LYoon STaskin B(2015)FinFET-Based Low-Swing ClockingACM Journal on Emerging Technologies in Computing Systems10.1145/270161712:2(1-20)Online publication date: 2-Sep-2015
https://dl.acm.org/doi/10.1145/2701617
Sitik CFilippini LSalman ETaskin B(2014)High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop DesignProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.53(498-503)Online publication date: 9-Jul-2014
https://dl.acm.org/doi/10.1109/ISVLSI.2014.53
Sitik CLerner STaskin B(2014)Timing characterization of clock buffers for clock tree synthesis2014 IEEE 32nd International Conference on Computer Design (ICCD)10.1109/ICCD.2014.6974686(230-236)Online publication date: Oct-2014
https://doi.org/10.1109/ICCD.2014.6974686
Sitik CTaskin B(2014)Iterative skew minimization for low swing clocksIntegration10.1016/j.vlsi.2013.10.00747:3(356-364)Online publication date: Jun-2014
https://doi.org/10.1016/j.vlsi.2013.10.007

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