research-article

Asymmetric-access aware optimization for STT-RAM caches with process variations

Authors:

Yi Zhou,

Chao Zhang,

Guangyu Sun,

Kun Wang,

Yu ZhangAuthors Info & Claims

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Pages 143 - 148

https://doi.org/10.1145/2483028.2483079

Published: 02 May 2013 Publication History

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Abstract

STT-RAM (Spin Transfer Torque Random Access Memory) has been extensively researched as a potential replacement of SRAM (Static RAM) as on-chip caches. Prior work has shown that STT-RAM caches can improve performance and reduce power consumption because of its advantages of high density, fast read speed, low standby power, etc. However, under the impact of process variations, using worst-case design can induce significant performance and power overhead in STT-RAM caches. In order to overcome the problem of process variations, we propose to apply the variable-latency access method to STT-RAM caches by introducing a variation-aware LRU (Least Recently Used) policy. Moreover, we show that simply applying traditional variable-latency access method is inefficient due to the read/write asymmetry. First, we demonstrate that a write-oriented data migration is preferred. Second, a block remapping is necessary to prevent some cache sets from being significantly affected by process variations. After using our techniques, the experimental results show that the performance can be improved by 13.8% and power consumption can be reduced by 14.1% compared to a prior approach [3].

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Salehi SKhoshavi NDeMara R(2020)Mitigating Process Variability for Non-Volatile Cache Resilience and YieldIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2018.27990058:3(724-737)Online publication date: 1-Jul-2020
https://doi.org/10.1109/TETC.2018.2799005
Chen FLi ZKang WZhao WLi HChen YShin Y(2018)Process variation aware data management for magnetic skyrmions racetrack memoryProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201653(221-226)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201653
Chen FLi ZKang WZhao WLi HChen Y(2018)Process variation aware data management for magnetic skyrmions racetrack memory2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297309(221-226)Online publication date: Jan-2018
https://doi.org/10.1109/ASPDAC.2018.8297309
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Index Terms

Asymmetric-access aware optimization for STT-RAM caches with process variations
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

May 2013

368 pages

ISBN:9781450320320

DOI:10.1145/2483028

General Chair:
Jose L. Ayala
Complutense University of Madrid, Spain
,
Program Chairs:
Alex Jones
University of Pittsburgh, USA
,
Patrick Madden
Binghamton University, USA
,
Publications Chair:
Ayse K. Coskun
Boston University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 May 2013

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GLSVLSI'13

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SIGDA

GLSVLSI'13: Great Lakes Symposium on VLSI 2013

May 2 - 3, 2013

Paris, France

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GLSVLSI '13 Paper Acceptance Rate 76 of 238 submissions, 32%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all

Salehi SKhoshavi NDeMara R(2020)Mitigating Process Variability for Non-Volatile Cache Resilience and YieldIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2018.27990058:3(724-737)Online publication date: 1-Jul-2020
https://doi.org/10.1109/TETC.2018.2799005
Chen FLi ZKang WZhao WLi HChen YShin Y(2018)Process variation aware data management for magnetic skyrmions racetrack memoryProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201653(221-226)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201653
Chen FLi ZKang WZhao WLi HChen Y(2018)Process variation aware data management for magnetic skyrmions racetrack memory2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297309(221-226)Online publication date: Jan-2018
https://doi.org/10.1109/ASPDAC.2018.8297309
Mittal S(2016)A Survey of Architectural Techniques for Managing Process VariationACM Computing Surveys10.1145/287116748:4(1-29)Online publication date: 9-Feb-2016
https://dl.acm.org/doi/10.1145/2871167
Cheshmikhani EMonazzah AFarbeh HMiremadi S(2016)Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches2016 12th European Dependable Computing Conference (EDCC)10.1109/EDCC.2016.10(120-129)Online publication date: Sep-2016
https://doi.org/10.1109/EDCC.2016.10
Kannan SKarimi NSinanoglu OKarri R(2015)Security Vulnerabilities of Emerging Nonvolatile Main Memories and CountermeasuresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.236974134:1(2-15)Online publication date: Jan-2015
https://doi.org/10.1109/TCAD.2014.2369741
Tsai HChen CYang KYang THuang LChung CChang MChen T(2014)Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store EliminationProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593153(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593153

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