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A fast handshake join implementation on FPGA with adaptive merging network

Published: 29 July 2013 Publication History

Abstract

One of a critical design issues for implementing handshake-join hardware is result collection performed by a merging network. To address the issue, we introduce an adaptive merging network. Our implementation achieves over 3 million tuples per second when the selectivity is 0.1. The proposed implementation attains up to 5.2x higher throughput than original handshake-join hardware. In this demonstration, we apply the proposed technique to filter out malicious packets from packet streams. To the best of our knowledge, our system is the fastest handshake join implementation on FPGA.

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Cited By

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  • (2017)Deadlock-free joins in DB-mesh, an asynchronous systolic array acceleratorProceedings of the 13th International Workshop on Data Management on New Hardware10.1145/3076113.3076118(1-8)Online publication date: 14-May-2017
  • (2014)Low-latency handshake joinProceedings of the VLDB Endowment10.14778/2732939.27329447:9(709-720)Online publication date: 1-May-2014
  • (2013)An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGAProceedings of the 2013 First International Symposium on Computing and Networking10.1109/CANDAR.2013.23(112-121)Online publication date: 4-Dec-2013

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cover image ACM Other conferences
SSDBM '13: Proceedings of the 25th International Conference on Scientific and Statistical Database Management
July 2013
401 pages
ISBN:9781450319218
DOI:10.1145/2484838
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 July 2013

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SSDBM '13

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Overall Acceptance Rate 56 of 146 submissions, 38%

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Cited By

View all
  • (2017)Deadlock-free joins in DB-mesh, an asynchronous systolic array acceleratorProceedings of the 13th International Workshop on Data Management on New Hardware10.1145/3076113.3076118(1-8)Online publication date: 14-May-2017
  • (2014)Low-latency handshake joinProceedings of the VLDB Endowment10.14778/2732939.27329447:9(709-720)Online publication date: 1-May-2014
  • (2013)An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGAProceedings of the 2013 First International Symposium on Computing and Networking10.1109/CANDAR.2013.23(112-121)Online publication date: 4-Dec-2013

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