research-article

Robust architectural support for transactional memory in the power architecture

Authors:

Harold W. Cain,

Maged M. Michael,

Derek Williams,

Hung LeAuthors Info & Claims

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

Pages 225 - 236

https://doi.org/10.1145/2485922.2485942

Published: 23 June 2013 Publication History

Abstract

On the twentieth anniversary of the original publication [10], following ten years of intense activity in the research literature, hardware support for transactional memory (TM) has finally become a commercial reality, with HTM-enabled chips currently or soon-to-be available from many hardware vendors. In this paper we describe architectural support for TM added to a future version of the Power ISA™. Two imperatives drove the development: the desire to complement our weakly-consistent memory model with a more friendly interface to simplify the development and porting of multithreaded applications, and the need for robustness beyond that of some early implementations. In the process of commercializing the feature, we had to resolve some previously unexplored interactions between TM and existing features of the ISA, for example translation shootdown, interrupt handling, atomic read-modify-write primitives, and our weakly consistent memory model. We describe these interactions, the overall architecture, and discuss the motivation and rationale for our choices of architectural semantics, beyond what is typically found in reference manuals.

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Cited By

Wan LChao FLi QHan J(2024)LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00081(865-875)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPS57955.2024.00081
Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Busch CChlebus BHerlihy MPopovic MPoudel PSharma G(2023)Flexible scheduling of transactional memory on treesTheoretical Computer Science10.1016/j.tcs.2023.114184(114184)Online publication date: Sep-2023
https://doi.org/10.1016/j.tcs.2023.114184
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cover image ACM Other conferences

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

June 2013

686 pages

ISBN:9781450320795

DOI:10.1145/2485922

General Chair:
Avi Mendelson
Technion

ACM SIGARCH Computer Architecture News Volume 41, Issue 3
ICSA '13
June 2013
666 pages
ISSN:0163-5964
DOI:10.1145/2508148
Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 June 2013

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ISCA'13: The 40th Annual International Symposium on Computer Architecture

June 23 - 27, 2013

Tel-Aviv, Israel

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ISCA '13 Paper Acceptance Rate 56 of 288 submissions, 19%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Wan LChao FLi QHan J(2024)LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00081(865-875)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPS57955.2024.00081
Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Busch CChlebus BHerlihy MPopovic MPoudel PSharma G(2023)Flexible scheduling of transactional memory on treesTheoretical Computer Science10.1016/j.tcs.2023.114184(114184)Online publication date: Sep-2023
https://doi.org/10.1016/j.tcs.2023.114184
Kim SHan MBaek W(2022)DPrime+DAbort: A High-Precision and Timer-Free Directory-Based Side-Channel Attack in Non-Inclusive Cache Hierarchies using Intel TSX2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00014(67-81)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00014
Poudel PSharma G(2021)Adaptive Versioning in Transactional Memory SystemsAlgorithms10.3390/a1406017114:6(171)Online publication date: 31-May-2021
https://doi.org/10.3390/a14060171
Ostrovsky OMorrison AGupta RShen X(2020)Scaling concurrent queues by using HTM to profit from failed atomic operationsProceedings of the 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3332466.3374511(89-101)Online publication date: 19-Feb-2020
https://dl.acm.org/doi/10.1145/3332466.3374511
Busch CHerlihy MPopovic MSharma G(2020)Dynamic Scheduling in Distributed Transactional Memory2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00094(874-883)Online publication date: May-2020
https://doi.org/10.1109/IPDPS47924.2020.00094
Dongol BJagadeesan RRiely JHollingsworth JKeidar I(2019)Modular transactionsProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295708(82-93)Online publication date: 16-Feb-2019
https://dl.acm.org/doi/10.1145/3293883.3295708
Shull TChoi JGarzaran MTorrellas J(2019)NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00054(412-425)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00054
Quislant RGutierrez EZapata EPlata O(2019)Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2019.04.018Online publication date: May-2019
https://doi.org/10.1016/j.jpdc.2019.04.018
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