research-article

JITPR: A framework for supporting fast application's implementation onto FPGAs

Authors:

Jürgen BeckerAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 6, Issue 2

Article No.: 7, Pages 1 - 12

https://doi.org/10.1145/2492185

Published: 02 August 2013 Publication History

Get Access

Abstract

The execution runtime usually is a headache for designers performing application mapping onto reconfigurable architectures. In this article we propose a methodology, as well as the supporting toolset, targeting to provide fast application implementation onto reconfigurable architectures with the usage of a Just-In-Time (JIT) compilation framework. Experimental results prove the efficiency of the introduced framework, as we reduce the execution runtime compared to the state-of-the-art approach on average by 53.5×. Additionally, the derived solutions achieve higher operation frequencies by 1.17×, while they also exhibit significant lower fragmentation ratios of hardware resources.

References

[1]

Betz, V., Rose, J., and Marquardt, A., Eds. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Norwell, MA.

Digital Library

Google Scholar

[2]

Flynn, A., Gordon-Ross, A., and George, A. 2009. Bitstream relocation with local clock domains for partially reconfigurable fpgas. In Proceedings of the Conference Exhibition on Design, Automation Test in Europe (DATE'09). 300--303.

Digital Library

Google Scholar

[3]

Gort, M. and Anderson, J. 2011. Reducing fpga router run-time through algorithm and architecture. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'11). 336--342.

Digital Library

Google Scholar

[4]

Hubner, M., Figuli, P., Girardey, R., Soudris, D., Siozios, K., and Becker, J. 2011. A heterogeneous multicore system on chip with run-time reconfigurable virtual fpga architecture. In Proceedings of the IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW'11). IEEE Computer Society, 143--149.

Digital Library

Google Scholar

[5]

Mcmurchie, L. and Ebeling, C. 1995. Pathfinder: A negotiation-based performance-driven router for fpgas. In Proceedings of the 3^rd ACM International Symposium on Field-Programmable Gate Arrays. (FPGA'95). ACM Press, New York, 111--117.

Digital Library

Google Scholar

[6]

Sidiropoulos, H., Siozios, K., and Soudris, D. 2012a. On supporting rapid exploration of memory hierarchies onto fpgas. J. Syst. Archit. Embed. Syst. Des. 59, 2, 78--90.

Digital Library

Google Scholar

[7]

Sidiropoulos, H., Siozios, K., Figuli, P., Soudris, D., and Hubner, M. 2012b. On supporting efficient partial reconfiguration with just-in-time compilation. In Proceedings of the 26^th IEEE International Parallel and Distributed Processing Symposium Workshops and PhD Forum (IPDPSW'12). 328--335.

Digital Library

Google Scholar

[8]

Silva, M. and Ferreira, J. 2008. Generation of partial fpga configurations at run-time. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'08). 367--372.

Google Scholar

[9]

Siozios, K., Soudris, D., and Thanailakis, A. 2010. A novel allocation methodology for partial and dynamic bitstream generation of fpga architectures. J. Circ. Syst. Comput. 19, 3, 701--717.

Crossref

Google Scholar

[10]

Tessier, R. 2002. Fast placement approaches for fpgas. ACM Trans. Des. Autom. Electron. Syst. 7, 2, 284--305.

Digital Library

Google Scholar

[11]

Wu, Q. and Mcelvain, K. S. 2012. A fast discrete placement algorithm for fpgas. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'12). ACM Press, New York, 115--118.

Digital Library

Google Scholar

[12]

Yang, S. 1991. Logic synthesis and optimization benchmarks user guide version 3.0. Tech. rep., Microcenter of North Carolina.

Google Scholar

Cited By

View all

Ferreira RRocha LSantos ANacif JWong SCarro L(2015)A Runtime FPGA Placement and Routing Using Low-Complexity Graph TraversalACM Transactions on Reconfigurable Technology and Systems10.1145/26607758:2(1-16)Online publication date: 17-Mar-2015
https://dl.acm.org/doi/10.1145/2660775

Index Terms

JITPR: A framework for supporting fast application's implementation onto FPGAs
1. Computer systems organization
  1. Architectures

Recommendations

Dynamic FPGA routing for just-in-time FPGA compilation
DAC '04: Proceedings of the 41st annual Design Automation Conference

Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. However, embedded systems increasingly incorporate Field Programmable Gate ...
Hardware accelerated FPGA placement

A key advantage of field-programmable gate arrays (FPGAs) over full-custom and semi-custom devices is that they provide relatively quick implementation from concept to physical realization. However, as modern FPGAs reach close to one million logic ...
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine
Special Section on Advances in Physical Design Automation and Regular Papers

Modern field-programmable gate array (FPGA) devices contain complex clock architectures on top of configurable logics. Unlike application specific integrated circuits (ASICs), the physical structure of clock networks in an FPGA is pre-manufactured and ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 6, Issue 2

Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)

July 2013

90 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2499625

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 August 2013

Accepted: 01 April 2013

Revised: 01 January 2013

Received: 01 September 2012

Published in TRETS Volume 6, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
188
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 17 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Ferreira RRocha LSantos ANacif JWong SCarro L(2015)A Runtime FPGA Placement and Routing Using Low-Complexity Graph TraversalACM Transactions on Reconfigurable Technology and Systems10.1145/26607758:2(1-16)Online publication date: 17-Mar-2015
https://dl.acm.org/doi/10.1145/2660775

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Dynamic FPGA routing for just-in-time FPGA compilation

Hardware accelerated FPGA placement

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine

Comments

Published In

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Dynamic FPGA routing for just-in-time FPGA compilation

Hardware accelerated FPGA placement

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine

Comments

Information

Published In

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Get Access

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations