research-article

Automatized high-level evaluation of security properties for RTL hardware designs

Authors:

Andrea Höller,

Christopher Preschern,

Christian Steger,

Christian Kreiner,

Josef HaidAuthors Info & Claims

WESS '13: Proceedings of the Workshop on Embedded Systems Security

Article No.: 6, Pages 1 - 8

https://doi.org/10.1145/2527317.2527323

Published: 29 September 2013 Publication History

Abstract

The ever increasing integration of embedded systems into our every lives created a strong demand for trustable software and hardware implementations. To provide such trust between manufacturer and customer of integrated systems, regulatory rules like the Common Criteria have been defined. While this international standard clearly prescribes the usage of formal methods at high assurance level, formal verification at code-level is not widespread in practice.

This work introduces a novel approach to verify the correct functionality of security critical hardware implementations under fault conditions. Generality is enabled by high-level evaluation using state machines extracted in an automatized way.

References

[1]

Common Criteria for Information Technology Security Evaluation Part 2 Version 3.1, 2012.

[2]

Z. Andraus and K. Sakallah. Automatic abstraction and verification of Verilog models. In Proceedings of the 41st annual Design Automation Conference, 2004.

Digital Library

[3]

T. Ball and S. Rajamani. Automatically validating temporal safety properties of interfaces. In Proceedings of the 8th international SPIN workshop on Model checking of software, pages 103--122. Springer-Verlag New York, Inc., 2001.

Digital Library

[4]

H. Bar-El, H. Choukri, D. Naccache, M. Tunstall, and C. Whelan. The sorcerer's apprentice guide to fault attacks. Proceedings of the IEEE, 94(2):370--382, 2006.

[5]

B. Beckert, D. Bruns, and S. Grebing. Mind the gap: Formal verification and the Common Criteria. International Verification Workshop, 2010.

[6]

I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase: an industry-oriented formal verification tool. In Proceedings of the 33rd annual Design Automation Conference. ACM, 1996.

Digital Library

[7]

J. Bei, H. Li, J. Bian, H. Xue, and X. Hong. Fsm modeling of synchronous vhdl design for symbolic model checking. In Proceedings of the ASP-DAC'99, 1999.

[8]

G. Beuster and K. Greimel. Developing a Formal Security Policy Model for a Smart Card EAL6 Evaluation. Presentation, 2011. International Common Criteria Conference.

[9]

G. Beuster and K. Greimel. Formal security policy models for smart card evaluations. Proceedings of the 27th Annual ACM Symposium on Applied Computing - SAC '12, 2012.

Digital Library

[10]

M. Boulé and Z. Zilic. Generating hardware assertion checkers: for hardware verification, emulation, post-fabrication debugging and on-line monitoring. Springer Verlag, 2008.

Digital Library

[11]

M. Bozzano and A. Villafiorita. The FSAP/NuSMV-SA safety analysis platform. International Journal on Software Tools for Technology Transfer (STTT), 9(1):5--24, 2007.

Digital Library

[12]

R. Brayton, G. Hachtel, A. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, et al. VIS: A system for verification and synthesis. In Computer Aided Verification, pages 428--432. Springer, 1996.

Digital Library

[13]

B. Chetali and Q. Nguyen. Industrial use of formal methods for a high-level security evaluation. FM 2008: Formal Methods, 2008.

Digital Library

[14]

P. Chu. RTL hardware design using VHDL: coding for efficiency, portability, and scalability. Wiley-IEEE Press, 2006.

Digital Library

[15]

D. Déharbe, S. Shankar, and E. Clarke. Model checking VHDL with CV. In Formal Methods in Computer-Aided Design. Springer, 1998.

Digital Library

[16]

J. Ezekiel and A. Lomuscio. Combining fault injection and model checking to verify fault tolerance in multi-agent systems. In Proceedings of The 8th International Conference on Autonomous Agents and Multiagent Systems-Volume 1, pages 113--120, 2009.

Digital Library

[17]

S. Graf and H. Saïdi. Construction of abstract state graphs with PVS. In Computer aided verification, pages 72--83. Springer, 1997.

Digital Library

[18]

M. Huth and M. Ryan. Logic in Computer Science: Modelling and reasoning about systems. Cambridge University Press, 2006.

[19]

A. Karputkin, R. Ubar, M. Tombak, and J. Raik. Automated correction of design errors by edge redirection on High-Level Decision Diagrams. In Quality Electronic Design (ISQED), 2012 13th International Symposium on, pages 686--693. IEEE, 2012.

[20]

A. Krieg, C. Bachmann, J. Grinschgl, C. Steger, R. Weiss, and J. Haid. Acceleration of fault attack emulation by consideration of fault propagation. In Field-Programmable Technology (FPT), 2012 International Conference on, pages 239 -- --242. IEEE, 2012.

[21]

S. Lahiri, S. Seshia, and R. Bryant. Modeling and verification of out-of-order microprocessors in UCLID. In Formal Methods in Computer-Aided Design, pages 142--159. Springer, 2002.

Digital Library

[22]

J. Lohse, J. Bormann, M. Payer, and G. Venzl. VHDL-translation for BDD-based formal verification. 1994.

[23]

S. Morimoto, S. Shigematsu, Y. Goto, and J. Cheng. Formal verification of security specifications with common criteria. In Proceedings of the 2007 ACM symposium on Applied computing, SAC '07, pages 1506--1512. ACM, 2007.

Digital Library

[24]

D. Moundanos, J. A. Abraham, and Y. Heskote. A unified framework for design validation and manufacturing test. In Test Conference. IEEE, 1996.

Digital Library

Cited By

Krieg CRathmair MSchupfer F(2014)A Process for the Detection of Design-Level Hardware Trojans Using Verification MethodsProceedings of the 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS)10.1109/HPCC.2014.112(729-734)Online publication date: 20-Aug-2014
https://dl.acm.org/doi/10.1109/HPCC.2014.112
Höller AKajtazovic NPreschern CKreiner C(2014)Formal Fault Tolerance Analysis of Algorithms for Redundant Systems in Early Design StagesSoftware Engineering for Resilient Systems10.1007/978-3-319-12241-0_6(71-85)Online publication date: 2014
https://doi.org/10.1007/978-3-319-12241-0_6

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cover image ACM Conferences

WESS '13: Proceedings of the Workshop on Embedded Systems Security

September 2013

71 pages

ISBN:9781450321457

DOI:10.1145/2527317

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 29 September 2013

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Bundesministerium für Verkehr, Innovation und Technologie

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ESWEEK'13

Sponsor:

ESWEEK'13: Ninth Embedded System Week

September 29 - October 4, 2013

Quebec, Montreal, Canada

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WESS '13 Paper Acceptance Rate 8 of 21 submissions, 38%;

Overall Acceptance Rate 8 of 21 submissions, 38%

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Cited By

Krieg CRathmair MSchupfer F(2014)A Process for the Detection of Design-Level Hardware Trojans Using Verification MethodsProceedings of the 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS)10.1109/HPCC.2014.112(729-734)Online publication date: 20-Aug-2014
https://dl.acm.org/doi/10.1109/HPCC.2014.112
Höller AKajtazovic NPreschern CKreiner C(2014)Formal Fault Tolerance Analysis of Algorithms for Redundant Systems in Early Design StagesSoftware Engineering for Resilient Systems10.1007/978-3-319-12241-0_6(71-85)Online publication date: 2014
https://doi.org/10.1007/978-3-319-12241-0_6

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