research-article

A programmable memory controller for the DDRx interfacing standards

Authors:

Mahdi Nazm Bojnordi,

Engin IpekAuthors Info & Claims

ACM Transactions on Computer Systems (TOCS), Volume 31, Issue 4

Article No.: 11, Pages 1 - 31

https://doi.org/10.1145/2534845

Published: 20 December 2013 Publication History

Abstract

Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable—a proven technique that has seen wide use in other control tasks, ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware.

This article presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable memory controller that can meet the performance requirements of a high-speed DDRx interface. The proposed controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the average performance of PARDIS comes within 8% of fixed-function hardware for each of these techniques; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6 to 17% and reduces DRAM energy by 9 to 22% over four existing memory controllers.

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Cited By

Wijeratne SPattnaik SChen ZKannan RPrasanna V(2021)Programmable FPGA-based Memory Controller2021 IEEE Symposium on High-Performance Interconnects (HOTI)10.1109/HOTI52880.2021.00020(43-51)Online publication date: Aug-2021
https://doi.org/10.1109/HOTI52880.2021.00020
Wang CMa HLiu SLi YRuan ZNguyen KBond MNetravali RKim MXu GLu SHowell J(2020)SemeruProceedings of the 14th USENIX Conference on Operating Systems Design and Implementation10.5555/3488766.3488781(261-280)Online publication date: 4-Nov-2020
https://dl.acm.org/doi/10.5555/3488766.3488781
Khoshavi NMaghsoudloo MBi YFrancois WJaimes LSargolzaei A(2020)A survey on attack vectors in stack cache memoryIntegration10.1016/j.vlsi.2020.02.004Online publication date: Feb-2020
https://doi.org/10.1016/j.vlsi.2020.02.004
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Index Terms

A programmable memory controller for the DDRx interfacing standards
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers
2. Computer systems organization
  1. Architectures
  2. Embedded and cyber-physical systems
    1. Embedded systems

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cover image ACM Transactions on Computer Systems

ACM Transactions on Computer Systems Volume 31, Issue 4

December 2013

90 pages

ISSN:0734-2071

EISSN:1557-7333

DOI:10.1145/2542150

Editor:
Todd C. Mowry

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Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 20 December 2013

Accepted: 01 June 2013

Revised: 01 June 2013

Received: 01 December 2012

Published in TOCS Volume 31, Issue 4

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Cited By

Wijeratne SPattnaik SChen ZKannan RPrasanna V(2021)Programmable FPGA-based Memory Controller2021 IEEE Symposium on High-Performance Interconnects (HOTI)10.1109/HOTI52880.2021.00020(43-51)Online publication date: Aug-2021
https://doi.org/10.1109/HOTI52880.2021.00020
Wang CMa HLiu SLi YRuan ZNguyen KBond MNetravali RKim MXu GLu SHowell J(2020)SemeruProceedings of the 14th USENIX Conference on Operating Systems Design and Implementation10.5555/3488766.3488781(261-280)Online publication date: 4-Nov-2020
https://dl.acm.org/doi/10.5555/3488766.3488781
Khoshavi NMaghsoudloo MBi YFrancois WJaimes LSargolzaei A(2020)A survey on attack vectors in stack cache memoryIntegration10.1016/j.vlsi.2020.02.004Online publication date: Feb-2020
https://doi.org/10.1016/j.vlsi.2020.02.004
Balakrishnan NBytheway TCarata LChick OSnee JAkoush SSohan RSeltzer MHopper AMissier PZhao J(2015)Recent advances in computer architectureProceedings of the 7th USENIX Conference on Theory and Practice of Provenance10.5555/2814579.2814587(8-8)Online publication date: 8-Jul-2015
https://dl.acm.org/doi/10.5555/2814579.2814587
PAN GLAI CJOU JLAI B(2015)Power-Efficient Instancy Aware DRAM SchedulingIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E98.A.942E98.A:4(942-953)Online publication date: 2015
https://doi.org/10.1587/transfun.E98.A.942

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