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Power estimation tool for system on programmable chip based platforms (abstract only)

Published: 26 February 2014 Publication History
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  • Abstract

    The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to estimate power/energy at an earlier phase of design flow. There are very few tools that addresses the design space exploration issue based on power and energy. In this paper, we propose a virtual platform based standalone power and energy estimation tool for System-on-Programmable Chip (SoPC) embedded platforms, which is independent of in-house tools. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for the different parts of the system. This is a onetime activity. In the second step, a simulation based virtual platform framework is developed to evaluate accurately the activities used in the related power models developed in the first step. The combination of the two steps lead to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed tool is also scalable for exploring complex embedded multi-core architectures.
    The effectiveness of our proposed tool is validated through dualcore RISC processor designed around the FPGA board and extended to accommodate futuristic multi-core processors for a reliable energy based design space exploration. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks such as Multimedia, EEMBC and SPEC2006. Estimated power values are compared to real board measurements and also to McPAT. Our obtained power/energy estimation results provide less than 9% of error for heterogeneous MPSoC based system and are 200% faster compared to other state-of-the-art power estimation tools.

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    1. Power estimation tool for system on programmable chip based platforms (abstract only)

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      cover image ACM Conferences
      FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
      February 2014
      272 pages
      ISBN:9781450326711
      DOI:10.1145/2554688
      Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 26 February 2014

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      Author Tags

      1. accuracy
      2. asic
      3. design space exploration
      4. fpga
      5. functional power models
      6. heterogeneous architecture
      7. multicore
      8. power/energy estimation
      9. speedup
      10. systemc
      11. tlm
      12. virtual platform

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      FPGA'14
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      FPGA '14 Paper Acceptance Rate 30 of 110 submissions, 27%;
      Overall Acceptance Rate 125 of 627 submissions, 20%

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