Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/2554688.2554761acmconferencesArticle/Chapter ViewAbstractPublication PagesfpgaConference Proceedingsconference-collections
research-article

MPack: global memory optimization for stream applications in high-level synthesis

Published: 26 February 2014 Publication History

Abstract

One of the challenges in designing high-performance FPGA applications is fine-tuning the use of limited on-chip memory storage among many buffers in an application. To achieve desired performance the designer faces the burden of packaging such buffers into on-chip memories and manually optimizing the utilization of each memory and the throughput of each buffer. In addition, the application memories may not match the word width or depth of the physical on-chip memories available on the FPGA. This process is time consuming and non-trivial, particularly with a large number of buffers of various depths and bit widths. We propose a tool, MPack, which globally optimizes on-chip memory use across all buffers for stream applications. The goal is to speed up development time by providing rapid design space exploration and relieving the designer of lengthy low-level iterations. We introduce new high-level pragmas allowing the user to specify global memory requirements, such as an application's on-chip memory budget and data throughput. We allow the user to quickly generate a large number of memory solutions and explore the trade-off between memory usage and achievable throughput. To demonstrate the effectiveness of our tool, we apply the new high-level pragmas to an image processing benchmark. MPack effectively explores the design space and is able to produce a large number of memory solutions ranging from 10 to 100% in throughput, and from 12 to 100% in on-chip memory usage.

References

[1]
E. H. Adelson et al. Pyramid methods in image processing. RCA engineer, 29(6):33--41, 1984.
[2]
D. Karchmer and J. Rose. Definition and solution of the memory packing problem for field-programmable systems. ICCAD, 1994.
[3]
H. Schmit and D. Thomas. Synthesis of application-specific memory designs. IEEE Trans. on VLSI Systems, 5(1):101--111, 1997.
[4]
Xilinx Inc. User Guide High-Level Synthesis, 2012.
[5]
Xilinx Inc. 7 Series FPGAs Memory Resources, 2013.

Cited By

View all
  • (2018)Breaking the Synchronization Bottleneck with Reconfigurable Transactional ExecutionIEEE Computer Architecture Letters10.1109/LCA.2018.282840217:2(147-150)Online publication date: 1-Jul-2018
  • (2015)Superoptimized Memory Subsystems for Streaming ApplicationsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689069(126-135)Online publication date: 22-Feb-2015

Index Terms

  1. MPack: global memory optimization for stream applications in high-level synthesis

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
    February 2014
    272 pages
    ISBN:9781450326711
    DOI:10.1145/2554688
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 26 February 2014

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. buffer packing
    2. fpga
    3. on-chip memory
    4. stream computing

    Qualifiers

    • Research-article

    Conference

    FPGA'14
    Sponsor:

    Acceptance Rates

    FPGA '14 Paper Acceptance Rate 30 of 110 submissions, 27%;
    Overall Acceptance Rate 125 of 627 submissions, 20%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)4
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 16 Oct 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2018)Breaking the Synchronization Bottleneck with Reconfigurable Transactional ExecutionIEEE Computer Architecture Letters10.1109/LCA.2018.282840217:2(147-150)Online publication date: 1-Jul-2018
    • (2015)Superoptimized Memory Subsystems for Streaming ApplicationsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689069(126-135)Online publication date: 22-Feb-2015

    View Options

    Get Access

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media