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Refresh pausing in DRAM memory systems

Authors:

Prashant J. Nair,

Chia-Chen Chou,

Moinuddin K. QureshiAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 11, Issue 1

Article No.: 10, Pages 1 - 26

https://doi.org/10.1145/2579669

Published: 01 February 2014 Publication History

Abstract

Dynamic Random Access Memory (DRAM) cells rely on periodic refresh operations to maintain data integrity. As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh. Refresh operations contend with read operations, which increases read latency and reduces system performance. We show that eliminating latency penalty due to refresh can improve average performance by 7.2%. However, simply doing intelligent scheduling of refresh operations is ineffective at obtaining significant performance improvement.

This article provides an alternative and scalable option to reduce the latency penalty due to refresh. It exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode. Therefore, a refresh operation has well-defined points at which it can potentially be Paused to service a pending read request. Leveraging this property, we propose Refresh Pausing, a solution that is highly effective at alleviating the contention from refresh operations. It provides an average performance improvement of 5.1% for 8Gb devices and becomes even more effective for future high-density technologies. We also show that Refresh Pausing significantly outperforms the recently proposed Elastic Refresh scheme.

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Cited By

Xiao YXiao GLiu KFu ZWang H(2023)Constraint Models of SDRAM-Based Arbitrary Waveform GeneratorIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2023.330935572(1-10)Online publication date: 2023
https://doi.org/10.1109/TIM.2023.3309355
Woo JSaileshwar GNair P(2023)Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10070999(374-389)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10070999
Yaglikci AOlgun APatel MLuo HHassan HOrosa LErgin OMutlu O(2022)HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00062(815-834)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00062
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Index Terms

Refresh pausing in DRAM memory systems
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 11, Issue 1

February 2014

373 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2591460

Issue’s Table of Contents

Copyright © 2014 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 February 2014

Accepted: 01 November 2013

Revised: 01 October 2013

Received: 01 June 2013

Published in TACO Volume 11, Issue 1

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Cited By

Xiao YXiao GLiu KFu ZWang H(2023)Constraint Models of SDRAM-Based Arbitrary Waveform GeneratorIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2023.330935572(1-10)Online publication date: 2023
https://doi.org/10.1109/TIM.2023.3309355
Woo JSaileshwar GNair P(2023)Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10070999(374-389)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10070999
Yaglikci AOlgun APatel MLuo HHassan HOrosa LErgin OMutlu O(2022)HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00062(815-834)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00062
Kim DKwon K(2020)Smart Adaptive Refresh for Optimum Refresh Interval Tracking using in-DRAM ECC2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS48704.2020.9184512(822-825)Online publication date: Aug-2020
https://doi.org/10.1109/MWSCAS48704.2020.9184512
Hassan HPatel MKim JYaglikci AVijaykumar NGhiasi NGhose SMutlu OManne SHunter HAltman E(2019)CROWProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322231(129-142)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322231
HAN MNA YJUNG DLEE HWOOK KIM SHAN Y(2018)Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLBIEICE Transactions on Electronics10.1587/transele.E101.C.170E101.C:3(170-182)Online publication date: 2018
https://doi.org/10.1587/transele.E101.C.170
Chalios CGeorgakoudis GTovletoglou KKarakonstantis GVandierendonck HNikolopoulos D(2018)DAREInternational Journal of High Performance Computing Applications10.1177/109434201771861232:1(74-88)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1177/1094342017718612
Hong SNair PAbali BBuyuktosunoglu AKim KHealy MOskin MInoue K(2018)AttachéProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00034(326-338)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00034
Ambriz-Vargas FCrespo-Villegas JZamorano-Ulloa RCabrera-Sierra RGómez-Yáñez C(2018)Point defect chemistry of donor-doped bismuth titanate ceramicJournal of Materials Science: Materials in Electronics10.1007/s10854-018-0552-5Online publication date: 14-Dec-2018
https://doi.org/10.1007/s10854-018-0552-5
Patel MKim JMutlu O(2017)The Reach Profiler (REAPER)ACM SIGARCH Computer Architecture News10.1145/3140659.308024245:2(255-268)Online publication date: 24-Jun-2017
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