research-article

Generation of reduced analog circuit models using transient simulation traces

Authors:

Paul Winkler,

Henda Aridhi,

Mohamed H. Zaki,

Sofiene TaharAuthors Info & Claims

GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI

Pages 305 - 310

https://doi.org/10.1145/2591513.2591530

Published: 20 May 2014 Publication History

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Abstract

The generation of fast models for device level circuit descriptions is a very active area of research. Model order reduction is an attractive technique for dynamical models size reduction. In this paper, we propose an approach based on clustering, curve-fitting, linearization and Krylov space projection to build reduced models for nonlinear analog circuits. We demonstrate our model order reduction method for three nonlinear circuits: a voltage controlled oscillator, an operational amplifier and a digital frequency divider. Our experimental results show that the reduced models lead to an improvement in simulation speed while guaranteeing the representation of the behavior of the original circuit design.

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Cited By

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Aridhi HZaki MTahar S(2016)Enhancing Model Order Reduction for Nonlinear Analog Circuit SimulationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.242145024:3(1036-1049)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2421450

Index Terms

Generation of reduced analog circuit models using transient simulation traces
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Published In

GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI

May 2014

376 pages

ISBN:9781450328166

DOI:10.1145/2591513

General Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Inst., USA
,
Program Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 May 2014

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GLSVLSI '14

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SIGDA

GLSVLSI '14: Great Lakes Symposium on VLSI 2014

May 21 - 23, 2014

Texas, Houston, USA

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GLSVLSI '14 Paper Acceptance Rate 49 of 179 submissions, 27%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

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Aridhi HZaki MTahar S(2016)Enhancing Model Order Reduction for Nonlinear Analog Circuit SimulationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.242145024:3(1036-1049)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2421450

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A compact CMOS current-mode analog multi-functions circuit

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