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Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization

Published: 01 June 2014 Publication History

Abstract

The challenge of equation-based analog synthesis comes from its dual nature: functions producing good least-square fits to SPICE-generated data are non-convex, hence not amenable to efficient optimization. In this paper, we leverage recent progress on Semidefinite Programming (SDP) relaxations of polynomial (non-convex) optimization. Using a general polynomial allows for much more accurate fitting of SPICE data compared to the more restricted functional forms. Recent SDP techniques for convex relaxations of polynomial optimizations are powerful but alone still insufficient: even for small problems, the resulting relaxations are prohibitively high dimensional.
We harness these new polynomial tools and realize their promise by introducing a novel regression technique that fits non-convex polynomials with a special sparsity structure. We show that the coupled sparse fitting and optimization (CSFO) flow that we introduce allows us to find accurate high-order polynomials while keeping the resulting optimization tractable.
Using established circuits for optimization experiments, we demonstrate that by handling higher-order polynomials we reduce fitting error to 3.6% from 10%, on average. This translates into a dramatic increase in the rate of constraint satisfaction: for a 1% violation threshold, the success rate is increased from 0% to 78%.

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cover image ACM Other conferences
DAC '14: Proceedings of the 51st Annual Design Automation Conference
June 2014
1249 pages
ISBN:9781450327305
DOI:10.1145/2593069
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2014

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  • (2024)Preference-Aware Constrained Multi-Objective Bayesian OptimizationProceedings of the 7th Joint International Conference on Data Science & Management of Data (11th ACM IKDD CODS and 29th COMAD)10.1145/3632410.3632427(182-191)Online publication date: 4-Jan-2024
  • (2024)High-Dimensional Analog Circuit Sizing via Bayesian Optimization in the Variational Autoencoder Enhanced Latent Space2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617489(193-197)Online publication date: 10-May-2024
  • (2024)A Survey on Smart Optimisation Techniques for 6G-oriented Integrated Circuits DesignMobile Networks and Applications10.1007/s11036-024-02343-7Online publication date: 16-May-2024
  • (2022)Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree SearchACM Transactions on Design Automation of Electronic Systems10.1145/354953828:2(1-33)Online publication date: 24-Dec-2022
  • (2022)CAD for Analog/Mixed‐Signal Integrated CircuitsAdvances in Semiconductor Technologies10.1002/9781119869610.ch3(43-60)Online publication date: 30-Sep-2022
  • (2021)A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local PenalizationProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431543(146-151)Online publication date: 18-Jan-2021
  • (2020)An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218592(1-6)Online publication date: Jul-2020
  • (2019)Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab ModelsProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317896(1-6)Online publication date: 2-Jun-2019
  • (2019)S2-PMProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287657(268-273)Online publication date: 21-Jan-2019
  • (2017)Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-LearningProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062235(1-6)Online publication date: 18-Jun-2017
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