On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking
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Abstract
This paper studies charged device model electrostatic discharge (CDM-ESD) events in die stacking process of 3D-ICs and investigates CDM-ESD protection circuits for individual TSVs to prevent high voltage stress on transistor connected to TSV. The models for power, area, delay, and signal integrity of TSVs considering ESD protection are presented. The models are used to drive a methodology to design reliable 3D-ICs considering CDM-ESD while minimizing the overheads. We study the impact of ESD protection on die-to-die asynchronous interface circuit.
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Index Terms
- On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking
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Published In
June 2014
1249 pages
ISBN:9781450327305
DOI:10.1145/2593069
Copyright © 2014 ACM.
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- EDAC: Electronic Design Automation Consortium
- SIGBED: ACM Special Interest Group on Embedded Systems
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE-CEDA
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Association for Computing Machinery
New York, NY, United States
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Published: 01 June 2014
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