research-article

Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches

Authors:

Abbas BanaiyanMofrad,

Puneet GuptaAuthors Info & Claims

DAC '14: Proceedings of the 51st Annual Design Automation Conference

Pages 1 - 6

https://doi.org/10.1145/2593069.2593184

Published: 01 June 2014 Publication History

Abstract

Complicated approaches to fault-tolerant voltage-scalable (FTVS) SRAM cache architectures can suffer from high overheads. We propose static (SPCS) and dynamic (DPCS) variants of power/capacity scaling, a simple and low-overhead fault-tolerant cache architecture that utilizes insights gained from our 45nm SOI test chip. Our mechanism combines multi-level voltage scaling with power gating of blocks that become faulty at each voltage level. The SPCS policy sets the runtime cache VDD statically such that almost all of the cache blocks are not faulty. The DPCS policy opportunistically reduces the voltage further to save more power than SPCS while limiting the impact on performance caused by additional faulty blocks. Through an analytical evaluation, we show that our approach can achieve lower static power for all effective cache capacities than a recent complex FTVS work. This is due to significantly lower overheads, despite the failure of our approach to match the min-VDD of the competing work at fixed yield. Through architectural simulations, we find that the average energy saved by SPCS is 55%, while DPCS saves an average of 69% of energy with respect to baseline caches at 1 V. Our approach incurs no more than 4% performance and 5% area penalties in the worst case cache configuration.

References

[1]

J. Abella et al. Low Vccmin Fault-Tolerant Cache with Highly Predictable Performance. In IEEE/ACM MICRO, 2009.

Digital Library

[2]

A. Agarwal et al. A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies. IEEE TVLSI, 2005.

Digital Library

[3]

A. Ansari et al. ZerehCache: Armoring Cache Architectures in High Defect Density Technologies. In IEEE/ACM MICRO, 2009.

Digital Library

[4]

A. Ansari et al. Archipelago: A Polymorphic Cache Design for Enabling Robust Near-Threshold Operation. In IEEE HPCA, 2011.

Digital Library

[5]

A. BanaiyanMofrad et al. FFT-Cache: A Flexible Fault-Tolerant Cache Architecture for Ultra Low Voltage Operation. In IEEE/ACM CASES, 2011.

Digital Library

[6]

N. Binkert et al. The gem5 Simulator. SIGARCH Comp. Arch. News, 2011.

Digital Library

[7]

B. Calhoun and A. Chandrakasan. A 256kb Sub-threshold SRAM in 65nm CMOS. In IEEE ISSCC, 2006.

[8]

L. Chang et al. Stable SRAM Cell Design for the 32nm Node and Beyond. In IEEE Symp. on VLSI Tech., 2005.

[9]

K. Flautner et al. Drowsy Caches: Simple Techniques for Reducing Leakage Power. In ACM/IEEE ISCA, 2002.

Digital Library

[10]

P. Gupta et al. Underdesigned and Opportunistic Computing in Presence of Hardware Variability. IEEE TCAD, 2013.

Digital Library

[11]

S. Hamdioui et al. March SS: A Test for All Static Simple RAM Faults. In IEEE MTDT, 2002.

Digital Library

[12]

J. Kim et al. Multi-Bit Error Tolerant Caches Using Two-Dimensional Error Coding. In IEEE/ACM MICRO, 2007.

Digital Library

[13]

C.-K. Koh et al. The Salvage Cache: A Fault-Tolerant Cache Architecture for Next-Generation Memory Technologies. In IEEE ICCD, 2009.

Digital Library

[14]

A. Kumar et al. SRAM Supply Voltage Scaling: A Reliability Perspective. In IEEE ISQED, 2009.

Digital Library

[15]

L. Lai and P. Gupta. Accurate and Inexpensive Performance Monitoring for Variability-Aware Systems. In ACM/IEEE ASP-DAC, 2014.

[16]

N. Muralimanohar et al. CACTI 6.0: A Tool to Model Large Caches. Technical report, HP Laboratories, 2009.

[17]

S. Ozdemir et al. Yield-Aware Cache Architectures. In IEEE/ACM MICRO, 2006.

Digital Library

[18]

M. Powell et al. Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. In IEEE/ACM ISLPED, 2000.

Digital Library

[19]

D. Rossi et al. Error Correcting Code Analysis for Cache Memory High Reliability and Performance. In DATE, 2011.

[20]

A. Sasan et al. A Fault Tolerant Cache Architecture for Sub 500mV Operation: Resizable Data Composer Cache (RDC-Cache). In ACM/IEEE CASES, 2009.

Digital Library

[21]

A. Sasan et al. History & Variation Trained Cache (HVT-Cache): A Process Variation Aware and Fine Grain Voltage Scalable Cache With Active Access History Monitoring. In IEEE ISQED, 2012.

[22]

P. Shirvani and E. McCluskey. PADded Cache: A New Fault-Tolerance Technique for Cache Memories. In IEEE VLSI Test Symp., 1999.

Digital Library

[23]

J. Wang and B. Calhoun. Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations. IEEE TVLSI, 2011.

Digital Library

[24]

N. H. E. Weste and D. M. Harris. CMOS VLSI Design: A Circuits and Systems Perspective. Addison-Wesley, 4th edition, 2011.

Digital Library

[25]

C. Wilkerson et al. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. In IEEE ISCA, 2008.

Digital Library

Cited By

Ganapathy SKalamatianos JBeckmann BRaasch SSzafaryn L(2019)Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00046(304-316)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00046
Salami BUnsal OKestelman A(2019)Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Undervolting Faults2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/EMPDP.2019.8671543(242-246)Online publication date: Feb-2019
https://doi.org/10.1109/EMPDP.2019.8671543
Filippou FKeramidas GMavropoulos MNikolos D(2018)A novel fault tolerant cache architecture based on orthogonal latin squares theory2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342236(1429-1434)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342236
Show More Cited By

Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Other conferences

DAC '14: Proceedings of the 51st Annual Design Automation Conference

June 2014

1249 pages

ISBN:9781450327305

DOI:10.1145/2593069

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGBED: ACM Special Interest Group on Embedded Systems
SIGDA: ACM Special Interest Group on Design Automation
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Published: 01 June 2014

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DAC '14

DAC '14: The 51st Annual Design Automation Conference 2014

June 1 - 5, 2014

CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Ganapathy SKalamatianos JBeckmann BRaasch SSzafaryn L(2019)Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00046(304-316)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00046
Salami BUnsal OKestelman A(2019)Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Undervolting Faults2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/EMPDP.2019.8671543(242-246)Online publication date: Feb-2019
https://doi.org/10.1109/EMPDP.2019.8671543
Filippou FKeramidas GMavropoulos MNikolos D(2018)A novel fault tolerant cache architecture based on orthogonal latin squares theory2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342236(1429-1434)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342236
Castro RWanner L(2018)A Framework for Variable Quality in Applications through Context-Aware Approximate Computing2018 VIII Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC.2018.00028(138-145)Online publication date: Nov-2018
https://doi.org/10.1109/SBESC.2018.00028
Salami BUnsal OCristal A(2018)A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00085(451-4511)Online publication date: Aug-2018
https://doi.org/10.1109/FPL.2018.00085
Wang JFu XZhang WZhang JQiu KLi T(2017)On the Implication of NTC versus Dark Silicon on Emerging Scale-Out Workloads: The Multi-Core Architecture PerspectiveIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.265424328:8(2314-2327)Online publication date: 1-Aug-2017
https://doi.org/10.1109/TPDS.2017.2654243
Navajothi RRahuman A(2017)Implementation of high performance 12T SRAM cell2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)10.1109/ICEICE.2017.8191902(1-6)Online publication date: Apr-2017
https://doi.org/10.1109/ICEICE.2017.8191902
Rahimi ABenini LGupta RRahimi ABenini LGupta R(2017)Memristive-Based Associative Memory for Approximate Computational ReuseFrom Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators10.1007/978-3-319-53768-9_11(165-179)Online publication date: 26-Apr-2017
https://doi.org/10.1007/978-3-319-53768-9_11
Mittal S(2016)A Survey of Architectural Techniques for Managing Process VariationACM Computing Surveys10.1145/287116748:4(1-29)Online publication date: 9-Feb-2016
https://dl.acm.org/doi/10.1145/2871167
Rahimi ABenini LGupta R(2016)Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to SoftwareProceedings of the IEEE10.1109/JPROC.2016.2518864104:7(1410-1448)Online publication date: Jul-2016
https://doi.org/10.1109/JPROC.2016.2518864
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