Cited By
View all- Kumawat RSahula VGaur M(2015)Modeling and synthesis of molecular memory2015 19th International Symposium on VLSI Design and Test10.1109/ISVDAT.2015.7208081(1-2)Online publication date: Jun-2015
Probabilistic modeling and analysis of molecular memory
Article No.: 6, Pages 1 - 16
Abstract
This article investigates the aspects of designing a nanocell based molecular memory. An empirical model for molecular device is developed, based on circuit behavior of nitro-substituted Oligo (Phynylene Ethynylene) molecule (OPE). This device model is subsequently used to design nanocell based 1-bit memory and verified using HSPICE. The approach is extended to train the nanocell for multibit storage capability using external voltage signals. It is observed that to successfully train a 2-bit molecular memory, the number of control signals should be approx. one-fourth of total number of nanoparticles. A computational framework is proposed to compute the probability of retrieving the stored data bits correctly, at the output terminal of the nanocell buffer. This nanocell configuration is simulated by systematically varying number of nanoparticles and molecular switches. It is observed that the probability of the existence of at least one path from input to output approaches close to unity with presence of 20 or more nanoparticles in a nanocell. During memory model validation, 1000 samples of 1-bit memory (consisting of 20 nanoparticles) were generated and verified for read and write operations. The model verification results obtained for this memory cell closely match those obtained using analytical solution of probabilistic graph model.
References
[1]
Chen, J., Reed, M. A., Rawlett, A. M., and Tour, J. M. 1999. Large on-off ratios and negative differential resistance in a molecular electronic device. Science 286, 5444, 1550--1552.
[2]
Chen, J., Wang, W., Reed, M. A., Rawlett, A. M., Price, D. W., and Tour, J. M. 2000. Room-temperature negative differential resistance in nanoscale molecular junctions. Appl. Phys. Lett. 77, 8.
[3]
Chen, Y., Jung, G., Ohlberg, D. A. A., Li, X., Stewart, D. R., Jeppesen, J. O., Nielsen, K. A., Fraser Stoddart, J., and Williams, R. S. 2003. Nanoscale molecular-switch crossbar circuits. Nanotechnology 14, 4, 462--468.
[4]
Cui, Y. and Lieber, C. 2001. Functional nanoscale electronic devices assembled using silicon nanowire building blocks. Science 291, 5505, 851--853.
[5]
Dehon, A. 2005. Nanowire-based programmable architectures. ACM J. Emerg. Technol. Comput. Syst. 1, 2, 109--162.
[6]
Green, J. E., Wook Choi, J., Boukai, A., et al. 2007. A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre. Nature 445, 414--417.
[7]
Huang, Y. 2001. Logic gates and computation from assembled nanowire building blocks. Science 294, 5545, 1313--1317.
[8]
Husband, C., Husband, S., Daniels, J., and Tour, J. 2003. Logic and memory with nanocell circuits. IEEE Trans. Electronic Devices 50, 9, 1865--1875.
[9]
Reed, M. A., Chen, J., Rawlett, A. M., Price, D. W., and Tour, J. M. 2001. Molecular random access memory cell. Appl. Phys. Lett. 78, 23.
[10]
Rose, G., Yuxing, Y., Tour, J. M., Cabe, A. C., Gergel-Hackett, N., Majumdar, N., Bean, J. C., Harriott L. R., and Stan, M. R. 2007. Designing cmos/molecular memories while considering device parameter variations. ACM J. Emerg. Technol. Comput. Syst. 3, 1.
[11]
Rose, G., Ziegler, M., and Stan, M. 2004. Large-signal two-terminal device model for nanoelectronic circuit analysis. IEEE Trans. VLSI Syst. 12, 11, 1201--1208.
[12]
Ross, S. M. 2007. Introduction to Probability Models 9th Ed. Academic Press.
[13]
Skoldberg, J., Onnheim, C., and Wendin, G. 2007. Nanocell devices and architecture for configurable computing with molecular electronics. IEEE Trans. Circuits Syst. 54, 11, 2461--2471.
[14]
Stan, M., Franzon, P., Goldstein, S., Lach, J., and Ziegler, M. 2003. Molecular electronics: from devices and interconnect to circuits and architecture. Proc. IEEE 91, 11, 1940--1957.
[15]
Tour, J., Van Zandt, W., Husband, C., Husband, S., Wilson, L., Franzon, P., and Nackashi, D. 2002. Nanocell logic gates for molecular computing. IEEE Trans. Nanotechnol. 1, 2, 100--109.
[16]
Wu, W., Jung, G.-Y., Olynick, D., et al. 2005. One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography. App. Phys. A 80, 1173--1178.
[17]
Zhong, Z., Wang, D., Cui, Y., Bockrath, M., and Lieber, C. M. 2003. Nanowire crossbar arrays as address decoders for integrated nanosystems. Science 302, 5649, 1377--1379.
[18]
Ziegler, M. M. and Stan, M. R. 2002. A case for cmos/nano co-design. In Proceedings of the IEEE International Conference on Computer-Aided Design. 348--352.
Index Terms
- Probabilistic modeling and analysis of molecular memory
Recommendations
Memory effect of a polymer thin-film transistor with self-assembled gold nanoparticles in the gate dielectric
A self-assembled film of gold nanoparticles is integrated into the gate dielectric of an organic thin-film transistor to produce memory effects. The transistor is fabricated on a heavily doped n-type silicon (n+-Si) substrate with a thermally grown ...
Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications
Silicon-oxide-nitride-oxide-silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO"xN"y metal oxide NPs embedded in the HfO"xN"...
Integration of organic insulator and self-assembled gold nanoparticles on Si MOSFET for novel non-volatile memory cells
Proceedings of the 29th international conference on micro and nano engineeringWe have fabricated a hybrid non-volatile gold nanoparticle floating-gate memory metal insulator semiconductor field effect transistor (MISFET) device combining silicon technology and organic thin film deposition. The nanoparticles are deposited by ...
Comments
Information & Contributors
Information
Published In
September 2014
142 pages
ISSN:1550-4832
EISSN:1550-4840
DOI:10.1145/2676581
- Editor:
- Krishnendu Chakrabarty
Copyright © 2014 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Publisher
Association for Computing Machinery
New York, NY, United States
Journal Family
Publication History
Published: 06 October 2014
Accepted: 01 March 2014
Revised: 01 December 2013
Received: 01 August 2013
Published in JETC Volume 11, Issue 1
Check for updates
Author Tags
Qualifiers
- Research-article
- Research
- Refereed
Funding Sources
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 158Total Downloads
- Downloads (Last 12 months)3
- Downloads (Last 6 weeks)1
Reflects downloads up to 15 Oct 2024
Other Metrics
Citations
Cited By
View all- Kumawat RSahula VGaur M(2015)Modeling and synthesis of molecular memory2015 19th International Symposium on VLSI Design and Test10.1109/ISVDAT.2015.7208081(1-2)Online publication date: Jun-2015
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in