research-article

NBTI tolerance and leakage reduction using gate sizing

Authors:

Tsung-Yi HoAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 11, Issue 1

Article No.: 4, Pages 1 - 12

https://doi.org/10.1145/2629657

Published: 06 October 2014 Publication History

Abstract

Leakage power is a major design constraint in deep submicron technology and below. Meanwhile, transistor degradation due to Negative Bias Temperature Instability (NBTI) has emerged as one of the main reliability concerns in nanoscale technology. Gate sizing is a widely used technique to reduce circuit leakage, and this approach has recently attracted much attention with regard to improving circuits to tolerate NBTI. However, these studies only consider timing and area constraints, and many other important issues, such as slew and max-load, are missing. In this article, we present an efficient gate sizing framework that can reduce leakage and improve circuit reliability under timing constraints. Our algorithms consider slack, slew and max-load constraints. The benchmarks are those from ISPD 2012, which feature industrial design properties, including discrete cell sizes, nonconvex cell timing models, slew dependencies and constraints, as well as large design sizes. The experimental results obtained from ISPD 2012 benchmark circuits demonstrate that our approach can meet all the constraints and tolerated NBTI degradation with a power savings of 6.54% as compared with the traditional method.

References

[1]

Bild, D. R., Bok, G. E., and Dick, R. P. 2009. Minimization of NBTI performance degradation using internal node control. In Proceedings of the ACM/IEEE Design, Automation and Test in Europe. 148--153.

Digital Library

[2]

Chen, C. P., Chu, C. C. N., and Wong, D. F. 1999. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. CAD 18, 7, 1014--1025.

Digital Library

[3]

Chen, Y.-P., Fang, J.-W., and Chang, Y.-W. 2007. ECO timing optimization using spare cells. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design. 530--535.

Digital Library

[4]

Chinnery, D. G. and Keutzer, K. 2005. Linear programming for sizing, V_th and V_dd assignment. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 149--154.

Digital Library

[5]

Calimera, A., Macii, E., and Poncino, M. 2009. NBTI-aware sleep transistor design for reliable power-gating. In Proceedings of the ACM Great Lakes Symposium on VLSI. 333--338.

Digital Library

[6]

Chandrakasan, A., Bowhill, W., and Fox, F. 2001. Design of High-Performance Microprocessor Circuits, IEEE Press.

Digital Library

[7]

Fleetwood, D. M., Zhang, E. X., Shen, X., Zhang, C. X., Schrimpf, R. D., and Pantelides, S. T. 2013. Bias-temperature instabilities in silicon carbide MOS devices. In Bias Temperature Instability for Devices and Circuits, Tibor Grasse Ed., Springer, 661--675.

[8]

Franco, J. and Kaczer, B. 2013. NBTI in (Si)Ge channel devices, In Bias Temperature Instability for Devices and Circuits, Tibor Grasse Ed., Springer, 615--641.

[9]

Franco, J., Kaczer, B., Cho, M., Eneman, G., Groeseneken G., and Grasser, T., 2010. Improvements of NBTI reliability in SiGe p-FETs. In Proceedings of International Reliability Physics Symposium, 1082--10845.

[10]

Huang, R., Wang, R., and Li, M. 2013. Characteristics of NBTI in Multi-gate FETs for Highly Scaled CMOS Technology. In Bias Temperature Instability for Devices and Circuits, Tibor Grasser Ed., Springer, 643--659.

[11]

Kang, K., Kufluoglu, H., Alam, M. A., and Roy, K. 2006. Efficient transistor-level sizing technique under temporal performance degradation due to NBTI. In Proceedings of the IEEE International Conference on Computer Design. 216--221.

[12]

Kang, K., Gangwal, S., Park, S., and Roy, K. 2008. NBTI induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution? In Proceedings of the ACM/IEEE Asian South Pacific Design Automation Conference. 726--731.

Digital Library

[13]

Kim T. H., Yu C. G., and Park, J. T. 2011. Concurrent NBTI and Hot-Carrier Degradation in p-Channel MuGFETs. IEEE Electron Device Lett. 32, 3, 294--296.

[14]

Kumar, S., Kim, C., and Sapatnekar, S. 2007. NBTI-aware synthesis of digital circuits. In Proceedings of the ACM/IEEE Design Automation Conference. 370--375.

Digital Library

[15]

Lillis, J., Cheng, C., and Lin, T. 1996. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid-State Circuits 31, 3, 437--447.

[16]

Liu, Y. and Hu, J. 2010. A new algorithm for simultaneous gate sizing and threshold voltage assignment. IEEE Trans. CAD 29, 2, 223--234.

Digital Library

[17]

Luo, T., Newmark, D., and Pan, D. Z. 2008. Total power optimization combining placement, sizing and multi-Vt through slack distribution management. In Proceedings of the ACM/IEEE Asian South Pacific Design Automation Conference. 352--357.

Digital Library

[18]

Lin, C.-H., Lin, I.-C., and Li, K.-H. 2011. TG-based technique for NBTI degradation and leakage optimization. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 133--138.

Digital Library

[19]

Lin, C.-H., Lin, I.-C., and Li, K.-H. 2013. Leakage and aging optimization using transmission gate-based technique. IEEE Trans. CAD 32, 1, 87--99.

Digital Library

[20]

Liu, C., Yu, T., Wang, R., Zhang, L., Huang, R., Kim, D.-W., Park, D., and Wang, Y. 2010. Negative-bias temperature instability in gate-all-around silicon nanowire MOSFETs: Characteristic modeling and the impact on circuit aging. IEEE Trans. Electron Devices, 57, 12, 3442--3450.

[21]

Ozdal, M. M., Amin, C., Ayupov, A., Burns, S., Wilke, G., and Zhuo, C. 2012. The ISPD-2012 discrete cell sizing contest and benchmark suite. In Proceedings of the International Symposium on Physical Design. 161--164. http://www.ispd.cc/contests/12/ispd2012_contest.html.

Digital Library

[22]

Ozdal, M. M., Burns, S., and Hu, J. 2011. Gate sizing and device technology selection algorithms for high performance industrial designs. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design. 724--731.

Digital Library

[23]

Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., and Roy, K. 2007. Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits. IEEE Trans. CAD. 26, 4, 743--751.

Digital Library

[24]

Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., and Roy, K. 2006. Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits. In Proceedings of the ACM/IEEE Design, Automation and Test in Europe. 780--785.

Digital Library

[25]

Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., and Roy, K. 2005. Impact of NBTI on the temporal performance degradation of digital circuits. IEEE Electron Device Lett. 26, 8, 560--562.

[26]

Reddy, V., Krishnan, A. T., Marshall, A., Rodriguez, J., Natarajan, S., Rost, T., and Krishnan, S. 2012. Impact of negative bias temperature instability on digital circuit reliability. In Proceedings of the IEEE International Reliability Physics Symposium. 248--253.

[27]

Schroder, D. K. 2009. Bias temperature instability in silicon carbide. In Proceedings of International Semiconductor Device Research Symposium. 1--2.

[28]

Vattikonda, R., Wang W., and Cao Y. 2006. Modeling and minimization of PMOS NBTI effect for robust nanometer design. In Proceedings of the ACM/IEEE Design Automation Conference. 1047--1052.

Digital Library

[29]

Wang, Y., Chen, X., Wang, W., and Cao, Y., Xie, Y., and Yang, H. 2011. Leakage power and circuit aging cooptimization by gate replacement techniques. IEEE Trans. VLSI 19, 4, 615--628.

Digital Library

[30]

Wang, J., Das, D., and Zhou, H. 2009. Gate sizing by lagrangian relaxation revisited. IEEE Trans. CAD 28, 7, 1071--1084.

Digital Library

[31]

Wang, W., Wei, Z., Yang, S., and Cao, Y. 2007. An efficient method to identify critical gates under circuit aging. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design. 735--740.

Digital Library

[32]

Wang W., Yang, S., Bhardwaj, S., Vattikonda, R., Vrudhula, S., Liu, F., and Cao, Y. 2007. The impact of NBTI on the performance of combinational and sequential circuits. In Proceedings of the ACM/IEEE Design Automation Conference. 364--369.

Digital Library

[33]

Yang, X. and Saluja, K. 2007. Combating NBTI degradation via gate sizing. In Proceedings of the IEEE International Symposium on Quality Electronic Design. 47--52.

Digital Library

Cited By

Kajal Sharma V(2024)NBTI Effect Survey for Low Power Systems in Ultra-NanoregimeCurrent Nanoscience10.2174/011573413725202323091905454720:3(298-313)Online publication date: May-2024
https://doi.org/10.2174/0115734137252023230919054547
Ghavami BRaji MIbrami MShannon L(2022)Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process VariationIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2022.317591422:3(371-380)Online publication date: Sep-2022
https://doi.org/10.1109/TDMR.2022.3175914
Aslam SJennions ISamie MPerinpanayagam SFang Y(2020)Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and MitigationIEEE Access10.1109/ACCESS.2020.29732608(31371-31397)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2973260
Show More Cited By

Index Terms

NBTI tolerance and leakage reduction using gate sizing
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering

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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 11, Issue 1

September 2014

142 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/2676581

Editor:
Krishnendu Chakrabarty
Duke University, USA

Issue’s Table of Contents

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 06 October 2014

Accepted: 01 February 2014

Revised: 01 December 2013

Received: 01 February 2013

Published in JETC Volume 11, Issue 1

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Cited By

Kajal Sharma V(2024)NBTI Effect Survey for Low Power Systems in Ultra-NanoregimeCurrent Nanoscience10.2174/011573413725202323091905454720:3(298-313)Online publication date: May-2024
https://doi.org/10.2174/0115734137252023230919054547
Ghavami BRaji MIbrami MShannon L(2022)Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process VariationIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2022.317591422:3(371-380)Online publication date: Sep-2022
https://doi.org/10.1109/TDMR.2022.3175914
Aslam SJennions ISamie MPerinpanayagam SFang Y(2020)Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and MitigationIEEE Access10.1109/ACCESS.2020.29732608(31371-31397)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2973260
Gomez AChampac V(2019)An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging EffectsJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05772-535:1(87-100)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s10836-019-05772-5
Huang SYeh HNieh Y(2015)Clock Period Minimization with Minimum Leakage PowerACM Transactions on Design Automation of Electronic Systems10.1145/277895421:1(1-33)Online publication date: 2-Dec-2015
https://dl.acm.org/doi/10.1145/2778954

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