research-article

An ID and Address Protection Unit for NoC based Communication Architectures

Authors:

Christophe BobdaAuthors Info & Claims

SIN '14: Proceedings of the 7th International Conference on Security of Information and Networks

Pages 288 - 294

https://doi.org/10.1145/2659651.2659719

Published: 09 September 2014 Publication History

Abstract

Security is becoming the primary concern in today's embedded systems. Network-on-Chip (NoC) based communication architectures have emerged as an alternative to shared bus mechanism in Multiprocessor System-on-Chip (MPSoC) devices, and the increasing number and functionality of processing cores has made such systems vulnerable to security attacks. In this paper an id and address verification (IAV) security module is presented, which is embedded in each router at the communication level. IAV verifies the identity and address range to be accessed by incoming and outgoing data packets in a NoC-based many-core shared memory architecture. Our IAV architecture is implemented on a FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyse the performance overhead for different network configurations. The proposed IAV module has reduced area and power consumption overhead when compared with similar existing solutions.

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Chacon GWilliams CKnechtel JSinanoglu OGratz PSoteriou V(2023)Coherence Attacks and Countermeasures in Interposer-based Chiplet SystemsACM Transactions on Architecture and Code Optimization10.1145/363346121:2(1-25)Online publication date: 20-Nov-2023
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Bobda CMbongue JSaha SAhmed M(2023)Domain Isolation and Access Control in Multi-tenant Cloud FPGAsSecurity of FPGA-Accelerated Cloud Computing Environments10.1007/978-3-031-45395-3_2(29-55)Online publication date: 18-Sep-2023
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Charles SBindschaedler VMishra P(2022)Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC ArchitecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.316760630:7(952-965)Online publication date: Jul-2022
https://doi.org/10.1109/TVLSI.2022.3167606
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SIN '14: Proceedings of the 7th International Conference on Security of Information and Networks

September 2014

518 pages

ISBN:9781450330336

DOI:10.1145/2659651

Conference Chair:
Ron Poet
University of Glasgow, UK
,
Program Chair:
Raj Muttukrishnan
City University, UK

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

SIGSAC: ACM Special Interest Group on Security, Audit, and Control
MNIT: Malaviya National Institute of Technology
Aksaray Univ.: Aksaray University
SICSA: The Scottish Informatics and Computer Science Alliance
University of Glasgow: University of Glasgow

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Association for Computing Machinery

New York, NY, United States

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Published: 09 September 2014

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SIN '14

SIN '14: The 7th International Conference on Security of Information and Networks

September 9 - 11, 2014

Scotland, Glasgow, UK

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SIN '14 Paper Acceptance Rate 32 of 109 submissions, 29%;

Overall Acceptance Rate 102 of 289 submissions, 35%

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https://dl.acm.org/doi/10.1145/3633461
Bobda CMbongue JSaha SAhmed M(2023)Domain Isolation and Access Control in Multi-tenant Cloud FPGAsSecurity of FPGA-Accelerated Cloud Computing Environments10.1007/978-3-031-45395-3_2(29-55)Online publication date: 18-Sep-2023
https://doi.org/10.1007/978-3-031-45395-3_2
Charles SBindschaedler VMishra P(2022)Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC ArchitecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.316760630:7(952-965)Online publication date: Jul-2022
https://doi.org/10.1109/TVLSI.2022.3167606
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