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Guaranteed Services of the NoC of a Manycore Processor

Published: 13 December 2014 Publication History
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  • Abstract

    The Kalray MPPA®-256 processor (Multi-Purpose Processing Array) integrates 256 processing engine (PE) cores and 32 resource management (RM) cores on a single 28nm CMOS chip. These cores are distributed across 16 compute clusters and 4 I/O subsystems. On-chip communications and synchronization are supported by an explicitly routed dual data & control network-on-chip (NoC), with one node per compute cluster and 4 nodes per I/O subsystem, for a total of 32 nodes. The data NoC is dedicated to streaming data transfers and may operate with guaranteed services, thanks to non-blocking routers and flow regulation at the source node. Its architecture has been designed so that (σ, ρ) network calculus applies with minimal approximations.
    Given a set of flows across this data NoC with predetermined routes, we formulate the problem of guaranteeing fair allocation of bandwidth across flows and we present bounds on the maximum transfer latency. By considering the architecture of the data NoC and by introducing conservative approximations, we show how this formulation can be transformed into a linear program. Solving this linear program is efficient and the quality of its solutions appears comparable to those of the original formulation, based on problem instances obtained from the cyclostatic dataflow compilation toolchain of the Kalray MPPA®-256 processor.

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    cover image ACM Other conferences
    NoCArc '14: Proceedings of the 2014 International Workshop on Network on Chip Architectures
    December 2014
    63 pages
    ISBN:9781450330640
    DOI:10.1145/2685342
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Publication History

    Published: 13 December 2014

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    NoCArc '14
    NoCArc '14: International Workshop on Network on Chip Architectures
    December 13 - 14, 2014
    Cambridge, United Kingdom

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    NoCArc '14 Paper Acceptance Rate 9 of 22 submissions, 41%;
    Overall Acceptance Rate 46 of 122 submissions, 38%

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    • (2023)Traffic Injection Regulation Protocol Based on Free Time-Slots Requests2023 IEEE 29th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA58653.2023.00027(157-166)Online publication date: 30-Aug-2023
    • (2022)Network Synthesis under Delay Constraints: The Power of Network Calculus DifferentiabilityIEEE INFOCOM 2022 - IEEE Conference on Computer Communications10.1109/INFOCOM48880.2022.9796777(1539-1548)Online publication date: 2-May-2022
    • (2021)Inter-kernel communication facility of a distributed operating system for NoC-based lightweight manycoresJournal of Parallel and Distributed Computing10.1016/j.jpdc.2021.04.002154(1-15)Online publication date: Aug-2021
    • (2021)A Configurable Hardware Architecture for Runtime Application of Network CalculusInternational Journal of Parallel Programming10.1007/s10766-021-00700-7Online publication date: 2-Apr-2021
    • (2021)A Configurable Hardware Architecture for Runtime Application of Network CalculusNetwork and Parallel Computing10.1007/978-3-030-79478-1_18(203-216)Online publication date: 23-Jun-2021
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    • (2019)On the Performance and Isolation of Asymmetric Microkernel Design for Lightweight Manycores2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC49506.2019.9046080(1-8)Online publication date: Nov-2019
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