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Compiler-Directed Power Management for Superscalars

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Ran GinosarAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 11, Issue 4

Article No.: 48, Pages 1 - 21

https://doi.org/10.1145/2685393

Published: 09 January 2015 Publication History

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Abstract

Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building a power delivery network for the worst-case power consumption is not energy efficient and often is impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this article, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core™ processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

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Cited By

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Yahya JVolos HBartolini DAntoniou GKim JWang ZKalaitzidis KRollet TChen ZGeng YMutlu OSazeides Y(2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00063(835-850)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00063
Yahya JKim JYaglikci APark JRotem ESazeides YMutlu O(2022)DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00089(1170-1183)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00089
Haj-Yahya JKim JYağlikçi APuddu IOrosa LLuna JAlser MMutlu OMartínez JDuato JJohn L(2021)IChannelsProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00081(985-998)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00081
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Index Terms

Compiler-Directed Power Management for Superscalars
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

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Reviews

Reviewer: R. Clayton

Modern processor architectures have complex, dynamic power demands that are difficult and expensive for the architecture's power distribution network (PDN) to meet. This paper describes a compiler-based analysis that delimits code regions having the potential to create exceptional power demands; the PDN reacts to these regions with actions that compensate for exceptional demand. System simulations show that delimited regions help the PDN reduce power overloads by 20 percent and overall power demand by 11 percent. This work addresses long-term (-104 nsec) voltage drops caused by capacitor exhaustion during high current demand. These problems are met by increasing supply, which spends power, or reducing demand, causing slower execution. A modified LLVM compiler performs static analysis over control-flow graphs to identify regions likely to cause problems. Individual instructions are assigned an empirical maximum energy use normalized to the cheapest instruction. The analysis identifies and minimizes code regions with excessive power demands; the remaining code is considered safe. A processor emulated the region-delimiting instruction and generated traces for offline simulator analysis. Tests based on SPEC CPU2006 benchmarks identified only power emergencies (no false negatives) with around 94 percent accuracy (six percent false-positive rate). The more precise false-positive rate improved average performance by around 12 percent. This paper (section 2 in particular) requires a good grasp of central processing unit (CPU) power management. The static analysis in section 3 is basic and can be easily picked up by a reader who understands the rudiments of compiler-based analysis. Online Computing Reviews Service

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 11, Issue 4

January 2015

797 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2695583

Editor:
Koen De Bosschere
Ghent University

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 09 January 2015

Accepted: 01 October 2014

Revised: 01 October 2014

Received: 01 June 2014

Published in TACO Volume 11, Issue 4

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https://doi.org/10.1109/MICRO56248.2022.00063
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https://doi.org/10.1109/HPCA53966.2022.00089
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Recommendations

The challenges of implementing fine-grained power gating

A performance-conserving approach for reducing peak power consumption in server systems

An experimental evaluation of real-time DVFS scheduling algorithms

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