article

Free access

RSIM: Rice simulator for ILP multiprocessors

Authors:

Vijay S. Pai,

Parthasarathy Ranganathan,

Sarita V. AdveAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 25, Issue 5

Page 1

https://doi.org/10.1145/271014.271015

Published: 01 December 1997 Publication History

PDF eReader

Abstract

No abstract available.

References

[1]

{1} V. S, Pal, P. Ranganthan, and S. V. Adve. RSIM Reference Manual, Version 1.0. Electrical and Computer Engineering Department, Rice University, August 1997. Technical Report 9705.

Google Scholar

[2]

{2} V. S. Pai, P. Ranganathan, and S. V. Adve. RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors. In Proceedings of the Third Workshop on Computer Architecture Education, February 1997: To appear in IEEE TCCA Newsletter, October 1997.

Google Scholar

Cited By

View all

Patel RKumar S(2018)Visualizing effect of dependency in superscalar pipelining2018 4th International Conference on Recent Advances in Information Technology (RAIT)10.1109/RAIT.2018.8388992(1-5)Online publication date: Mar-2018
https://doi.org/10.1109/RAIT.2018.8388992
Ahmed KLiu JBadawy AEidenbenz S(2017)A brief history of HPC simulation and future challenges2017 Winter Simulation Conference (WSC)10.1109/WSC.2017.8247804(419-430)Online publication date: Dec-2017
https://doi.org/10.1109/WSC.2017.8247804
Mellor-Crummey JGarvin J(2016)Optimizing Sparse Matrix–Vector Product Computations Using Unroll and JamThe International Journal of High Performance Computing Applications10.1177/109434200403895118:2(225-236)Online publication date: 26-Jul-2016
https://doi.org/10.1177/1094342004038951
Show More Cited By

Index Terms

RSIM: Rice simulator for ILP multiprocessors

Recommendations

RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors

The early 1990s saw several announcements of commercial shared-memory systems using processors that aggressively exploited instruction-level parallelism (ILP), including the MIPS R10000, Hewlett-Packard PA8000, and Intel Pentium Pro. These processors ...
An evaluation of speculative instruction execution on simultaneous multithreaded processors

Modern superscalar processors rely heavily on speculative execution for performance. For example, our measurements show that on a 6-issue superscalar, 93% of committed instructions for SPECINT95 are speculative. Without speculation, processor resources ...
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruction-level parallelism (ILP) and thread-level parallelism (TLP). Wide-issue super-scalar processors exploit ILP by executing multiple instructions from a ...

Comments

Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 25, Issue 5

Dec. 1997

14 pages

ISSN:0163-5964

DOI:10.1145/271014

Editor:
Doug DeGroot
Texas Instruments, Dallas

Issue’s Table of Contents

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 December 1997

Published in SIGARCH Volume 25, Issue 5

Check for updates

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

43
Total Citations
View Citations
214
Total Downloads

Downloads (Last 12 months)40
Downloads (Last 6 weeks)15

Reflects downloads up to 09 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Patel RKumar S(2018)Visualizing effect of dependency in superscalar pipelining2018 4th International Conference on Recent Advances in Information Technology (RAIT)10.1109/RAIT.2018.8388992(1-5)Online publication date: Mar-2018
https://doi.org/10.1109/RAIT.2018.8388992
Ahmed KLiu JBadawy AEidenbenz S(2017)A brief history of HPC simulation and future challenges2017 Winter Simulation Conference (WSC)10.1109/WSC.2017.8247804(419-430)Online publication date: Dec-2017
https://doi.org/10.1109/WSC.2017.8247804
Mellor-Crummey JGarvin J(2016)Optimizing Sparse Matrix–Vector Product Computations Using Unroll and JamThe International Journal of High Performance Computing Applications10.1177/109434200403895118:2(225-236)Online publication date: 26-Jul-2016
https://doi.org/10.1177/1094342004038951
Kamali HHessabi S(2016)AdapNoC: A fast and flexible FPGA-based NoC simulator2016 26th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2016.7577377(1-8)Online publication date: Aug-2016
https://doi.org/10.1109/FPL.2016.7577377
Mediouni NBen Abid SKallel OHasnaoui S(2015)SimEvents based high level early design space exploration and modeling of a 3D Network on Chip2015 10th International Design & Test Symposium (IDT)10.1109/IDT.2015.7396759(157-158)Online publication date: Dec-2015
https://doi.org/10.1109/IDT.2015.7396759
Mediouni NBen Abid SKallel OHasnaoui S(2015)High level NoC modeling using discrete event simulation2015 10th International Design & Test Symposium (IDT)10.1109/IDT.2015.7396752(143-144)Online publication date: Dec-2015
https://doi.org/10.1109/IDT.2015.7396752
Al-Manasia MChaczko Z(2015)An Overview of Chip Multi-Processors Simulators TechnologyProgress in Systems Engineering10.1007/978-3-319-08422-0_128(877-884)Online publication date: 2015
https://doi.org/10.1007/978-3-319-08422-0_128
Tatas KSiozios KSoudris DJantsch ATatas KSiozios KSoudris DJantsch A(2013)The Spidergon STNoCDesigning 2D and 3D Network-on-Chip Architectures10.1007/978-1-4614-4274-5_7(161-190)Online publication date: 9-Oct-2013
https://doi.org/10.1007/978-1-4614-4274-5_7
Sondag TPokorny KRajan H(2012)FrancesACM Transactions on Computing Education10.1145/2382564.238256612:4(1-31)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1145/2382564.2382566
Ren PLis MCho MShim KFletcher CKhan OZheng NDevadas S(2012)HORNETIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.218476031:6(890-903)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1109/TCAD.2012.2184760
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Abstract

References

Cited By

Index Terms

Recommendations

RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors

An evaluation of speculative instruction execution on simultaneous multithreaded processors

Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

Comments

Information

Published In

Publisher

Publication History

Check for updates

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Get Access

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations