research-article

Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures

Authors:

Sai Vineel Reddy Chittamuru,

Srinivas Desai,

Sudeep PasrichaAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 63 - 68

https://doi.org/10.1145/2742060.2742067

Published: 20 May 2015 Publication History

Abstract

On-chip communication is widely considered to be one of the major performance bottlenecks in contemporary chip multiprocessors (CMPs). With recent advances in silicon nanophotonics, photonic-based networks-on-chip (NoCs) are being considered as a viable option for communication in emerging CMPs as they can enable higher bandwidth and lower power dissipation compared to traditional electrical NoCs. In this paper, we present UltraNoC, a novel reconfigurable silicon-photonic NoC architecture that features improved channel sharing and supports dynamic re-prioritization and exchange of bandwidth between clusters of cores running multiple applications, to increase channel utilization and performance. Experimental results show that UltraNoC improves throughput by up to 9.8× while reducing latency by up to 55% and energy-delay product by up to 90% over state-of-the-art solutions.

References

[1]

R. Ho, et al., "The future of wires," in Proc. IEEE, Apr 2001.

[2]

W. J. Dally, B. Towles, "Route packets, not wires," in DAC, 2001.

[3]

S. Bahirat et al., "OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs," in ASPDAC, Yokohama, Japan, Jan 2011.

[4]

D. A. B. Miller, "Device requirements for optical interconnects to silicon chips," in IEEE, Special Issue on Silicon Photonics, 2009.

[5]

Q. Xu et al., "12.5gbit/s carrier-injection-based silicon micro-ring silicon modulators," in Optics Express, vol. 15, no. 2, Jan. 2007.

[6]

S. J. Koester et al., "Ge-on soi-detector/si-cmos-amplifier receivers for high-performance optical communication applications," in JLT, vol. 25, no. 1, pp. 46--57, Jan. 2007.

[7]

J. D. Owens, et al., "Research challenges for on-chip interconnection networks," in IEEE Micro, September-October 2007.

Digital Library

[8]

D. Vantrease et al., "Corona: System implications of emerging nanophotonic technology," in ISCA, 2008.

Digital Library

[9]

Y. Pan et al.,"Firefly: Illuminating future network-on-chip with nanophotonics," in ISCA, 2009.

Digital Library

[10]

Y. Pan, J. Kim, G. Memik, "Flexishare: Channel sharing for an energy efficient nanophotonic crossbar," in HPCA, 2010.

[11]

C. Chen, A. Joshi, "Runtime management of laser power in silicon-photonic multibus NoC architecture," in IEEE JQE, 2013.

[12]

V. Almeida et al., "All-optical switching on a silicon chip" in Optics Letters, 29:2867--2869, 2004.

[13]

C. A. Barrios, et al., "Low-power-consumption short-length and high-modulation-depth silicon electro-optic modulator" in JLT, 2003.

[14]

R. Morris et al., "Power-efficient and high-performance multilevel hybrid nanophotonic interconnect for multicores," in NOCS 2010.

Digital Library

[15]

J. Psota et al., "ATAC: On-chip optical networks for multicore processors," Boston Area Archit. Workshop, pp. 107--108, Jan. 2007.

[16]

C. Bienia et al., "The PARSEC Benchmark Suit: Characterization and Architectural Implications," in PACT, Oct. 2008.

Digital Library

[17]

M. J. Cianchettiet et al., "Phastlane: a rapid transit optical routing network," in ISCA, 2009.

Digital Library

[18]

N. Kirman et al., "A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing," in ASPLOS 2010.

Digital Library

[19]

X. Zheng et al., "Ultra-efficient 10Gb/s hybrid integrated silicon photonic transmitter and receiver," in Opt. Express, Mar 2011.

[20]

M. Petracca, et al., "Design exploration of optical interconnection networks for chip multiprocessors," in HOTI, Aug. 2008,

Digital Library

[21]

A. Joshi et al., "Silicon-Photonic Clos Networks for Global On-Chip Communication", in NOCS 2009

Digital Library

[22]

D. Vantrease et al., "Light speed arbitration and flow control for nanophotonic interconnects," in IEEE/ACM MICRO, Dec. 2009.

Digital Library

[23]

P. Grani and S. Bartolini, "Design Options for Optical Ring Interconnect in Future Client Devices," in ACM JETC, May, 2014.

Digital Library

[24]

T. Pimpalkhute et al., "An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors," in ISQED 2014.

[25]

N. Binkert et al.,"The gem5 Simulator," in CA News, May 2011.

Digital Library

Cited By

Karempudi VSunny FThakkar IChittamuru SNikdast MPasricha S(2022)Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative StudyACM Journal on Emerging Technologies in Computing Systems10.1145/348736518:3(1-36)Online publication date: 22-Mar-2022
https://dl.acm.org/doi/10.1145/3487365
Pasricha SNikdast M(2020)A Survey of Silicon Photonics for Energy-Efficient Manycore ComputingIEEE Design & Test10.1109/MDAT.2020.298262837:4(60-81)Online publication date: Aug-2020
https://doi.org/10.1109/MDAT.2020.2982628
Pasricha SChittamuru SThakkar IChen DHomayoun HTaskin B(2018)Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-ChipProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194608(317-322)Online publication date: 30-May-2018
https://dl.acm.org/doi/10.1145/3194554.3194608
Show More Cited By

Index Terms

Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures
1. General and reference
  1. Cross-computing tools and techniques
    1. Design
2. Networks
  1. Network properties
    1. Network structure

Recommendations

SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast-Enabled Channel Sharing for Multicore Architectures

On-chip communication is widely considered to be one of the major performance bottlenecks in contemporary chip multiprocessors (CMPs). With recent advances in silicon nanophotonics, photonics-based network-on-chip (NoC) architectures are being ...
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
ISCA '10

Scaling trends of logic, memories, and interconnect networks lead towards dense many-core chips. Unfortunately, process yields and reticle sizes limit the scalability of large single-chip systems. Multi-chip systems break free of these areal limits, but ...
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

Scaling trends of logic, memories, and interconnect networks lead towards dense many-core chips. Unfortunately, process yields and reticle sizes limit the scalability of large single-chip systems. Multi-chip systems break free of these areal limits, but ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IEEE CEDA
IEEE CASS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 May 2015

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Badges

Best Paper

Author Tags

Qualifiers

Research-article

Funding Sources

SRC, National Science Foundation
Air Force Office of Scientific Research

Conference

GLSVLSI '15

Sponsor:

SIGDA

GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

Acceptance Rates

GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Upcoming Conference

GLSVLSI '25

Sponsor:
sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

17
Total Citations
View Citations
1,255
Total Downloads

Downloads (Last 12 months)339
Downloads (Last 6 weeks)55

Reflects downloads up to 08 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Karempudi VSunny FThakkar IChittamuru SNikdast MPasricha S(2022)Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative StudyACM Journal on Emerging Technologies in Computing Systems10.1145/348736518:3(1-36)Online publication date: 22-Mar-2022
https://dl.acm.org/doi/10.1145/3487365
Pasricha SNikdast M(2020)A Survey of Silicon Photonics for Energy-Efficient Manycore ComputingIEEE Design & Test10.1109/MDAT.2020.298262837:4(60-81)Online publication date: Aug-2020
https://doi.org/10.1109/MDAT.2020.2982628
Pasricha SChittamuru SThakkar IChen DHomayoun HTaskin B(2018)Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-ChipProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194608(317-322)Online publication date: 30-May-2018
https://dl.acm.org/doi/10.1145/3194554.3194608
Chittamuru SThakkar IPasricha S(2018)HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.274996726:1(168-181)Online publication date: Jan-2018
https://doi.org/10.1109/TVLSI.2017.2749967
Chittamuru SThakkar IPasricha S(2018)LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-ChipIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2018.28462744:4(758-772)Online publication date: 1-Oct-2018
https://doi.org/10.1109/TMSCS.2018.2846274
Thakkar IPasricha S(2018)Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling2018 Ninth International Green and Sustainable Computing Conference (IGSC)10.1109/IGCC.2018.8752130(1-7)Online publication date: Oct-2018
https://doi.org/10.1109/IGCC.2018.8752130
Yao KYe YPasricha SXu JParameswaran S(2017)Thermal-sensitive design and power optimization for a 3D torus-based optical NoCProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199811(827-834)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199811
Chittamuru SDesai SPasricha S(2017)SWIFTNoCACM Journal on Emerging Technologies in Computing Systems10.1145/306051713:4(1-27)Online publication date: 29-Jun-2017
https://dl.acm.org/doi/10.1145/3060517
Reddy Chittamuru SThakkar IPasricha S(2017)Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)10.1109/SLIP.2017.7974906(1-8)Online publication date: 27-Jun-2017
https://doi.org/10.1109/SLIP.2017.7974906
Kennedy MKodi A(2017)Laser Pooling: Static and Dynamic Laser Power Allocation for On-Chip Optical InterconnectsJournal of Lightwave Technology10.1109/JLT.2017.268196035:15(3159-3167)Online publication date: 1-Aug-2017
https://doi.org/10.1109/JLT.2017.2681960
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten