research-article

b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units

Authors:

G. Tziantzioulis,

N. Hardavellas,

S. Ogrenci-Memik,

S. ParthasarathyAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 105, Pages 1 - 6

https://doi.org/10.1145/2744769.2744805

Published: 07 June 2015 Publication History

Abstract

Existing timing error models for voltage-scaled functional units ignore the effect of history and correlation among outputs, and the variation in the error behavior at different bit locations. We propose b-HiVE, a model for voltage-scaling-induced timing errors that incorporates these attributes and demonstrates their impact on the overall model accuracy. On average across several operations, b-HiVE's estimation is within 1--3% of comprehensive analog simulations, which corresponds to 5--17x higher accuracy (6--10x on average) than error models currently used in approximate computing research. To the best of our knowledge, we present the first bit-level error models of arithmetic units, and the first error models for voltage scaling of bitwise logic operations and floating-point units.

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Cited By

Chatzitsompanis GKarakonstantis G(2023)On the Facilitation of Voltage Over-Scaling and Minimization of Timing Errors in Floating-Point Multipliers2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS59296.2023.10224887(1-7)Online publication date: 3-Jul-2023
https://doi.org/10.1109/IOLTS59296.2023.10224887
Tompazi SKarakonstantis G(2023)Microarchitecture-Aware Timing Error Prediction via Deep Neural Networks2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS59296.2023.10224868(1-8)Online publication date: 3-Jul-2023
https://doi.org/10.1109/IOLTS59296.2023.10224868
Tompazi SKarakonstantis G(2023)A Compressed and Accurate Sparse Deep Learning-based Workload-Aware Timing Error Model2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00012(9-12)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00012
Show More Cited By

Index Terms

b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 07 June 2015

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National Science Foundation

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DAC '15

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Chatzitsompanis GKarakonstantis G(2023)On the Facilitation of Voltage Over-Scaling and Minimization of Timing Errors in Floating-Point Multipliers2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS59296.2023.10224887(1-7)Online publication date: 3-Jul-2023
https://doi.org/10.1109/IOLTS59296.2023.10224887
Tompazi SKarakonstantis G(2023)Microarchitecture-Aware Timing Error Prediction via Deep Neural Networks2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS59296.2023.10224868(1-8)Online publication date: 3-Jul-2023
https://doi.org/10.1109/IOLTS59296.2023.10224868
Tompazi SKarakonstantis G(2023)A Compressed and Accurate Sparse Deep Learning-based Workload-Aware Timing Error Model2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00012(9-12)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00012
Ma DZhang XHuang KJiang YChang WJiao X(2022)DEVoT: Dynamic Delay Modeling of Functional Units Under Voltage and Temperature VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307697041:4(827-839)Online publication date: Apr-2022
https://doi.org/10.1109/TCAD.2021.3076970
Assare OGupta R(2022)Performance Analysis of Timing-Speculative ProcessorsIEEE Transactions on Computers10.1109/TC.2021.305187771:2(407-420)Online publication date: 1-Feb-2022
https://doi.org/10.1109/TC.2021.3051877
Tompazi STsiokanos IMartinez del-Rincon JMukhanov LKarakonstantis G(2022)Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations2022 IEEE 40th International Conference on Computer Design (ICCD)10.1109/ICCD56317.2022.00074(455-462)Online publication date: Oct-2022
https://doi.org/10.1109/ICCD56317.2022.00074
Tsiokanos IPapadimitriou GGizopoulos DKarakonstantis G(2022)Hardware Level ApproximationsApproximate Computing Techniques10.1007/978-3-030-94705-7_3(43-79)Online publication date: 3-Jan-2022
https://doi.org/10.1007/978-3-030-94705-7_3
Bagheriye LKwisthout J(2021)Brain-Inspired Hardware Solutions for Inference in Bayesian NetworksFrontiers in Neuroscience10.3389/fnins.2021.72808615Online publication date: 2-Dec-2021
https://doi.org/10.3389/fnins.2021.728086
Tsiokanos IPapadimitriou GGizopoulos DKarakonstantis G(2021)Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors2021 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC53511.2021.00022(125-137)Online publication date: Nov-2021
https://doi.org/10.1109/IISWC53511.2021.00022
Tsiokanos IMukhanov LGeorgakoudis GNikolopoulos DKarakonstantis G(2020)DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116363(1121-1126)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116363
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