research-article

Towards enhancing analog circuits sizing using SMT-based techniques

Authors:

Mohamed H. Zaki,

Sofiène TaharAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 171, Pages 1 - 6

https://doi.org/10.1145/2744769.2744919

Published: 07 June 2015 Publication History

Abstract

This paper presents an approach for enhancing analog circuit sizing using Satisfiability Modulo Theory (SMT). The circuit sizing problem is encoded using nonlinear constraints. An SMT-based algorithm exhaustively explores the design space, where the biasing-level design variables are conservatively tracked using a collection of hyperrectangles. The device dimensions are then determined by accurately relating biasing to geometry-level design parameters. We demonstrate the feasibility and efficiency of the proposed methodology on a two-stage amplifier and a folded cascode amplifier. Experimental results show that our approach can achieve higher quality in analog synthesis and unrivaled coverage of the design space.

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Cited By

Muthamizh Vithagan KSundaresha VViraraghavan J(2023)Geometric Programming Approach to Glitch Minimization via Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320797042:6(1988-2001)Online publication date: Jun-2023
https://doi.org/10.1109/TCAD.2022.3207970
Rao VSavidis I(2019)Mesh Based Obfuscation of Analog Circuit Properties2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702671(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702671
Lahiouel OZaki MTahar S(2018)Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving TechniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265180737:3(517-530)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2651807
Show More Cited By

Index Terms

Towards enhancing analog circuits sizing using SMT-based techniques
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Published: 07 June 2015

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Muthamizh Vithagan KSundaresha VViraraghavan J(2023)Geometric Programming Approach to Glitch Minimization via Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320797042:6(1988-2001)Online publication date: Jun-2023
https://doi.org/10.1109/TCAD.2022.3207970
Rao VSavidis I(2019)Mesh Based Obfuscation of Analog Circuit Properties2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702671(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702671
Lahiouel OZaki MTahar S(2018)Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving TechniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265180737:3(517-530)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2651807
Rao VSavidis I(2018)Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS.2018.8605710(102-106)Online publication date: Oct-2018
https://doi.org/10.1109/APCCAS.2018.8605710
Lahiouel OZaki MTahar S(2017)Enhancing analog yield optimization for variation-aware circuits sizingProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130679(1273-1276)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130679
Lahiouel OZaki MTahar S(2017)Enhancing analog yield optimization for variation-aware circuits sizingDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927187(1273-1276)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927187

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