research-article

A Survey on Chip to System Reverse Engineering

Authors:

Shahed E. Quadir,

Navid Asadizanjani,

Sina Shahbazmohamadi,

Mark TehranipoorAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 13, Issue 1

Article No.: 6, Pages 1 - 34

https://doi.org/10.1145/2755563

Published: 13 April 2016 Publication History

Abstract

The reverse engineering (RE) of electronic chips and systems can be used with honest and dishonest intentions. To inhibit RE for those with dishonest intentions (e.g., piracy and counterfeiting), it is important that the community is aware of the state-of-the-art capabilities available to attackers today. In this article, we will be presenting a survey of RE and anti-RE techniques on the chip, board, and system levels. We also highlight the current challenges and limitations of anti-RE and the research needed to overcome them. This survey should be of interest to both governmental and industrial bodies whose critical systems and intellectual property (IP) require protection from foreign enemies and counterfeiters who possess advanced RE capabilities.

References

[1]

Robert J. Abella, James M. Daschbach, and Roger J. McNichols. 1994. Reverse engineering industrial applications. Computers and Industrial Engineering 26, 2, 381--385.

Digital Library

[2]

Jason Abt and Chris Pawlowicz. 2012. Circuit Analysis Techniques: Delayering and Circuit Vision. Available at http://www.techinsights.com/.

[3]

Actel. 2002. Design Security in Nonvolatile Flash and Antifuse FPGAs. Retrieved March 19, 2016, from http://www.actel.com/documents/DesignSecurity_WP.pdf.

[4]

Alldatasheet. 2014. Electronic Components Datasheet Search. Retrieved March 19, 2016, from http://www.alldatasheet.com/.

[5]

Answers.com. 2014. IC Construction. Available at http://www.answers.com/topic/dual-in-line-package.

[6]

N. Asadizanjani, S. Shahbazmohamadi, and E. H. Jordan. 2014. Investigation of surface geometry change in thermal barrier coatings using computed x-ray tomography. In Proceedings of the 38th International Conference and Expo on Advanced Ceramics and Composites (ICACC’14).

[7]

C. Bao, D. Forte, and A. Srivastava. 2014. On application of one-class SVM to reverse engineering-based hardware Trojan detection. In Proceedings of the 2014 15th International Symposium on Quality Electronic Design (ISQED’14). IEEE, Los Alamitos, CA, 47--54.

[8]

G. K. Bartley, T. A. Christensen, P. E. Dahlen, and E. S. John II. 2011. Implementing tamper evident and resistant detection through modulation of capacitance. US Patent 7,989,918.

[9]

James P. Baukus, Lap-Wai Chow, William M. Clark Jr., and Gavin J. Harbison. 2005. Use of silicon block process step to camouflage a false transistor. US Patent 6,979,606.

[10]

Alex Baumgarten, Akhilesh Tyagi, and Joseph Zambreno. 2010. Preventing IC piracy using reconfigurable logic barriers. IEEE Design and Test of Computers 27, 1, 66--75.

Digital Library

[11]

Friedrich Beck. 1998. Integrated Circuit Failure Analysis: A Guide to Preparation Techniques. John Wiley & Sons.

[12]

L. Benini, E. Omerbegovic, A. Macii, M. Poncino, E. Macii, and F. Pro. 2003. Energy-aware design techniques for differential power analysis protection. In Proceedings of the Design Automation Conference. IEEE, Los Alamitos, CA, 36--41.

Digital Library

[13]

F. Benz, A. Seffrin, and S. A. Huss. 2012. Bil: A tool-chain for bitstream reverse-engineering. In Proceedings of the 2012 22nd International Conference on Field Programmable Logic and Applications (FPL’12). IEEE, Los Alamitos, CA, 735--738.

[14]

Bharat Bhushan, Harald Fuchs, and Masahiko Tomitori. 2008. Applied Scanning Probe Methods X: Biomimetics and Industrial Applications. Vol. 9. Springer.

[15]

Ted J. Biggerstaff. 1989. Design recovery for maintenance and reuse. Computer 22, 7, 36--49.

Digital Library

[16]

Christian Boit, Clemens Helfmeier, and Uwe Kerst. 2013. Security risks posed by modern IC debug and diagnosis tools. In Proceedings of the 2013 Workshop on Fault Diagnosis and Tolerance in Cryptology (FDTC’13). IEEE, Los Alamitos, CA, 3--11.

Digital Library

[17]

Eric Brier, Christophe Clavier, and Francis Olivier. 2004. Correlation power analysis with a leakage model. In Cryptographic Hardware and Embedded Systems—CHES 2004. Lecture Notes in Computer Science, Vol. 3156. Springer, 16--29.

[18]

Brightsight. 2014. Physical Attacks on Cryptographic Devices. Retrieved March 19, 2016, from http://www.lirmm.fr/socsip/images2/stories/colloque2014/vanbattum.pdf.

[19]

Britannica.com. 2014. Integrated Circuit (IC). Retrieved March 19, 2016, from http://www.britannica.com/EBchecked/topic/289645/integrated-circuit-IC.

[20]

Hyouk-Kyu Cha, Ilhyun Yun, Jinbong Kim, Byeong-Cheol So, Kanghyup Chun, Ilku Nam, and Kwyro Lee. 2006. A 32-kb standard CMOS antifuse one-time programmable ROM embedded in a 16-bit microcontroller. IEEE Journal of Solid-State Circuits 41, 9, 2115--2124.

[21]

Rajat S. Chakraborty and Swarup Bhunia. 2009. HARPOON: An obfuscation-based SoC design methodology for hardware protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 10, 1493--1502.

Digital Library

[22]

CTI. 2013. Counterfeit Components Avoidance Program. Retrieved March 19, 2016, from http://www.cti-us.com/CCAP.htm.

[23]

Shane K. Curtis, Stephen P. Harston, and Christopher A. Mattson. 2011. The fundamentals of barriers to reverse engineering and their implementation into mechanical components. Research in Engineering Design 22, 4, 245--261.

[24]

DatasheetCatalog. 2013. Datasheet. Available at http://www.datasheetcatalog.com/.

[25]

C. De Nardi, R. Desplats, P. Perdu, F. Beaudoin, and J. L. Gauffier. 2005. Oxide charge measurements in EEPROM devices. Microelectronics Reliability 45, 9, 1514--1519.

[26]

C. De Nardi, R. Desplats, P. Perdu, J. L. Gauffier, and C. Guérin. 2006a. Descrambling and data reading techniques for flash-EEPROM memories. Application to smart cards. Microelectronics Reliability 46, 9, 1569--1574.

[27]

C. De Nardi, R. Desplats, P. Perdu, C. Guérin, J. L. Gauffier, and T. B. Amundsen. 2006b. Direct measurements of charge in floating gate transistor channels of flash memories using scanning capacitance microscopy. In Proceedings of the International Symposium for Testing and Failure Analysis, Vol. 32. 86.

[28]

Avinash R. Desai, Michael S. Hsiao, Chao Wang, Leyla Nazhandali, and Simin Hall. 2013. Interlocking obfuscation for anti-tamper hardware. In Proceedings of the 8th Annual Cyber Security and Information Intelligence Research Workshop (CSIIRW’13). ACM, New York, NY, 8.

Digital Library

[29]

DoD. 2014. DoD Anti-Tamper Executive Agent. Retrieved March 19, 2016, from https://at.dod.mil/content/short-course.

[30]

Saar Drimer. 2008. Volatile FPGA design security—a survey. In IEEE Computer Society Annual Volume. IEEE, Los Alamitos, CA, 292--297.

[31]

Saar Drimer. 2009. Security for Volatile FPGAs. Rapport Technique UCAM-CLTR-763. Computer Laboratory, University of Cambridge.

[32]

Fujitsu. 2014. FRAM Structure. Retrieved March 19, 2016, from http://www.fujitsu.com/us/products/devices/semiconductor/memory/fram/overview/structure/.

[33]

B. Gassend, D. Clarke, M. Van Dijk, and S. Devadas. 2002. Silicon physical random functions. In Proceedings of the 9th ACM Conference on Computer and Communications Security. ACM, New York, NY, 148--160.

Digital Library

[34]

GE. 2014. Inspection and NDT. Available at https://www.gemeasurement.com/inspection-and-non-destructive-testing.

[35]

Swaroop Ghosh, Abhishek Basak, and Swarup Bhunia. 2014. How secure are printed circuit boards against Trojan attacks? IEEE Design and Test 32, 2, 7--16.

[36]

Joe Grand. 2014. Printed circuit board deconstruction techniques. In Proceedings of the 8th USENIX Conference on Offensive Technologies. 11.

Digital Library

[37]

Tanaka Group. 2011. Bonding Wires by Tanaka Precious Metals. Retrieved March 19, 2016, from http://pro.tanaka.co.jp/en/solution/main-product/product06/.

[38]

U. Guin, D. DiMase, and M. Tehranipoor. 2014a. A comprehensive framework for counterfeit defect coverage analysis and detection assessment. Journal of Electronic Testing 30, 1, 25--40.

Digital Library

[39]

U. Guin, D. DiMase, and M. Tehranipoor. 2014b. Counterfeit integrated circuits: Detection, avoidance, and the challenges ahead. Journal of Electronic Testing 30, 1, 9--23.

Digital Library

[40]

U. Guin, K. Huang, D. DiMase, J. M. Carulli, M. Tehranipoor, and Y. Makris. 2014. Counterfeit integrated circuits: A rising threat in the global semiconductor supply chain. Proceedings of the IEEE 102, 8, 1207--1228.

[41]

Mark C. Hansen, Hakan Yalcin, and John P. Hayes. 1999. Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering. IEEE Design and Test of Computers 16, 3, 72--80.

Digital Library

[42]

Ben Johnson. 2013. EE368: Reverse Engineering of Printed Circuit Boards. Retrieved March 19, 2016, from https://stacks.stanford.edu/file/druid:np318ty6250/Johnson_Reverse_Engineering_PCBs.pdf.

[43]

R. Joshi and B. J. Shanker. 1996. Plastic chip carrier package. In Proceedings of the 46th Electronic Components and Technology Conference. IEEE, Los Alamitos, CA, 772--776.

[44]

Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim. 2009. A study of through-silicon-via impact on the 3d stacked IC layout. In Proceedings of the 2009 International Conference on Computer-Aided Design. ACM, New York, NY, 674--680.

Digital Library

[45]

Oliver Kömmerling and Markus G. Kuhn. 1999. Design principles for tamper-resistant smartcard processors. In Proceedings of the USENIX Workshop on Smartcard Technology, Vol. 12. 9--20.

Digital Library

[46]

Farinaz Koushanfar. 2011. Integrated circuits metering for piracy protection and digital rights management: An overview. In Proceedings of the 21st Great Lakes Symposium on VLSI. ACM, New York, NY, 449--454.

Digital Library

[47]

C. Koutsougeras, N. Bourbakis, and V. J. Gallardo. 2002. Reverse engineering of real PCB level design using Verilog HDL. International Journal of Engineering Intelligent Systems for Electrical Engineering and Communications 10, 2, 63--68.

[48]

Stephen Ledford. 2004. Non-Volatile Memory Technology Overview. Technical Report. Non-Volatile Memory Technology Center, Austin, TX.

[49]

W. Li, A. Gascon, P. Subramanyan, W. Y. Tan, A. Tiwari, S. Malik, N. Shankar, and S. A. Seshia. 2013. WordRev: Finding word-level structures in a sea of bit-level gates. In Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST’13). IEEE, Los Alamitos, CA, 67--74.

[50]

W. Li, Z. Wasson, and S. A. Seshia. 2012. Reverse engineering circuits using behavioral pattern mining. In Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST’12). IEEE, Los Alamitos, CA, 83--88.

[51]

Jim Lipman. 2014. Why Replacing ROM with 1T-OTP Makes Sense. Retrieved March 19, 2016, from http://www.chipestimate.com/tech-talks/2008/03/11/Sidense-Why-Replacing-ROM-with-1T-OTP-Makes-Sense.

[52]

Harold G. Longbotham, Ping Yan, Hemal N. Kothari, and Jun Zhou. 1995. Nondestructive reverse engineering of trace maps in multilayered PCBs. In AUTOTESTCON’95. Systems Readiness: Test Technology for the 21st Century. Conference Record. IEEE, Los Alamitos, CA, 390--397.

[53]

Roel Maes, Dries Schellekens, Pim Tuyls, and Ingrid Verbauwhede. 2009. Analysis and design of active IC metering schemes. In Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust (HOST’09). IEEE, Los Alamitos, CA, 74--81.

Digital Library

[54]

Ruzinoor C. Mat, Shahrul Azmi, Ruslizam Daud, Abdul N. Zulkifli, and Farzana K. Ahmad. 2006. Morphological Operation on Printed Circuit Board (PCB) Reverse Engineering Using MATLAB. Available at http://repo.uum.edu.my/2417/.

[55]

Maxim Integrated. 2014. Glossary Term: Printed-Circuit-Board. Retrieved March 19, 2016, from http://www.maximintegrated.com/en/glossary/definitions.mvp/term/Printed-Circuit-Board/gpk/973.

[56]

Ian McLoughlin. 2008. Secure embedded systems: The threat of reverse engineering. In Proceedings of the 14th IEEE International Conference on Parallel and Distributed Systems (ICPADS’08). IEEE, Los Alamitos, CA, 729--736.

Digital Library

[57]

Hannes Mio and Franz Kreupl. 2008. IC chip with nanowires. US Patent 7,339,186.

[58]

Amir Moradi, Markus Kasper, and Christof Paar. 2012. Black-box side-channel attacks highlight the importance of countermeasures. In Topics in Cryptology—CT-RSA 2012. Springer, 1--18.

Digital Library

[59]

Amir Moradi, Alessandro Barenghi, Timo Kasper, and Christof Paar. 2011. On the vulnerability of FPGA bitstream encryption against power analysis attacks: Extracting keys from Xilinx Virtex-II FPGAs. In Proceedings of the 18th ACM Conference on Computer and Communications Security (CCS’11). ACM, New York, NY, 111--124.

Digital Library

[60]

B. N. Naveen and K. S. Raghunathan. 1993. An automatic netlist-to-schematic generator. IEEE Design and Test of Computers 10, 1, 36--41.

Digital Library

[61]

Nikon. 2013. Microscopy. Retrieved March 19, 2016, from http://www.microscopyu.com/.

[62]

Jean-Baptiste Note and Éric Rannaud. 2008. From the bitstream to the netlist. In Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA’08). 264--264.

Digital Library

[63]

NREL. 2014. Scanning Kelvin Probe Microscopy. Retrieved March 19, 2016, from http://www.nrel.gov/pv/measurements/scanning_kelvin.html.

[64]

Xiaochuan Pan. 1998. Unified reconstruction theory for diffraction tomography, with consideration of noise control. Journal of the Optical Society of America: A 15, 9, 2312--2326.

[65]

Matteo Patelmo and Bruno Vajana. 2001. Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication. US Patent 6614080 B2.

[66]

Gregory Phipps. 2005. Wire bond vs. flip chip packaging. Advanced Packaging Magazine 14, 7, 28.

[67]

Purdue.edu. 2014. Scanning Electron Microscope. Retrieved March 19, 2016, from http://www.purdue.edu/ehps/rem/rs/sem.htm.

[68]

Gregory A. Quirk. 2013. Under the Hood: TI 65-nm chip at heart of Nokia 2610. Retrieved March 19, 2016, from http://www.eetimes.com/document.asp?doc_id=1281289.

[69]

Business Insider. 2012. The Chinese Navy Is Betting Big On Its New Submarine Hunting Drones. Retrieved March 19, 2016, from http://www.businessinsider.com/chinese-drones-reverse-engineered-to-hunt-submarines-2012-4.

[70]

M. Rahman, D. Forte, Q. Shi, G. K. Contreras, and M. Tehranipoor. 2014. CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly. In Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’14). IEEE, Los Alamitos, CA, 46--51.

[71]

Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, and Ramesh Karri. 2012. Security analysis of logic obfuscation. In Proceedings of the 49th Annual Design Automation Conference. ACM, New York, NY, 83--89.

Digital Library

[72]

Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, and Ramesh Karri. 2013. Security analysis of integrated circuit camouflaging. In Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security. ACM, New York, NY, 709--720.

Digital Library

[73]

Jarrod A. Roy, Farinaz Koushanfar, and Igor L. Markov. 2008a. EPIC: Ending piracy of integrated circuits. In Proceedings of the Conference on Design, Automation, and Test in Europe. ACM, New York, NY, 1069--1074.

Digital Library

[74]

Jarrod A. Roy, Farinaz Koushanfar, and Igor L. Markov. 2008b. Protecting bus-based hardware IP by secret sharing. In Proceedings of the 45th Annual Design Automation Conference. ACM, New York, NY, 846--851.

Digital Library

[75]

Shared Resources. 2014. Transmission Electron Microscope (TEM). Retrieved March 19, 2016, from http://sharedresources.fhcrc.org/services/transmission-electron-microscopy-tem.

[76]

EESemi. 2013. Wet Etching Recipes. Retrieved March 19, 2016, from http://www.eesemi.com/etch_recipes.htm.

[77]

Sergei Skorobogatov. 2005a. Data remanence in flash memory devices. In Cryptographic Hardware and Embedded Systems—CHES 2005. Springer, 339--353.

Digital Library

[78]

Sergei Skorobogatov. 2005b. Semi-Invasive Attacks: A New Approach to Hardware Security Analysis. University of Cambridge.

[79]

Space Photonics. 2013. Anti-Tamper Technology. Retrieved March 19, 2016, from http://www.spacephotonics.com/Anti_Tamper_Systems_Materials.php.

[80]

Bernd Stamme. 2014. Anti-fuse memory provides robust, secure NVM option. (08 2014). http://www.eetimes.com/document.asp?doc_id=1279746.

[81]

Francois-Xavier Standaert. 2008. Secure and efficient implementation of symmetric encryption schemes using FPGAs. In Cryptographic Engineering. Springer, 295.

[82]

François-Xavier Standaert, Tal G. Malkin, and Moti Yung. 2006. A Formal Practice-Oriented Model for the Analysis of Side-Channel Attacks. Report 2006/139. Cryptology ePrint Archive.

[83]

Stanford.edu. 2014. Stanford Microscopy Facility. Retrieved March 19, 2016, from https://microscopy.stanford.edu/.

[84]

P. Subramanyan, N. Tsiskaridze, K. Pasricha, D. Reisman, A. Susnea, and S. Malik. 2013. Reverse engineering digital circuits using functional analysis. In Proceedings of the Conference on Design, Automation, and Test in Europe. 1277--1280.

Digital Library

[85]

Swarthmore.edu. 2005. CMOS Inverter Cross Section. Retrieved March 19, 2016, from http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/.

[86]

Pawel Swierczynski, Amir Moradi, David Oswald, and Christof Paar. 2013. Physical security evaluation of the bitstream encryption mechanism of Altera Stratix II and Stratix III FPGAs. ACM Transactions on Reconfigurable Technology and Systems 7, 4, Article No. 34.

Digital Library

[87]

SypherMedia. 2012. Circuit Camouflage Technology. Retrieved March 19, 2016, from http://www.smi.tv/SMI_SypherMedia_Library_Intro.pdf.

[88]

Christopher Tarnovsky. 2010. Deconstructing a ‘Secure’ Processor. Retrieved March 19, 2016, from https://www.youtube.com/watch?v=w7PT0nrK2BE.

[89]

TechInsights. 2014. Sony Xperia Play Teardown and Analysis. Retrieved March 19, 2016, from http://www.techinsights.com/teardowns/sony-xperia-play-teardown/.

[90]

Texas Instruments. 2014. Marking Convention. Retrieved March 19, 2016, from http://focus.ti.com/quality/docs/gencontent.tsp?templateId=5909&navigationId==12626&contentId==153966.

[91]

Priya Thanigai. 2014. Introducing Advanced Security to Low-Power Applications with FRAM-Based MCUs. Retrieved March 19, 2016, from http://www.ecnmag.com/articles/2014/03/introducing-advanced-security-low-power-applications-fram-mcus.

[92]

Kris Tiri and Ingrid Verbauwhede. 2004. A Dynamic and Differential CMOS Logic Style to Resist Power and Timing Attacks on Security IC’s. Report 2004/066. IACR ePrint Archive.

[93]

Randy Torrance and Dick James. 2009. The state-of-the-art in IC reverse engineering. In Cryptographic Hardware and Embedded Systems—CHES 2009. Springer, 363--381.

Digital Library

[94]

J. A. Van Geloven, P. T. Tuyls, R. A. Wolters, and N. Verhaegh. 2012. Tamper-resistant semiconductor device and methods of manufacturing thereof. US Patent 8,143,705.

[95]

Virage Logic. 2014. Reverse Engineering Techniques in CMOS Based Non-Volatile Memory (NVM). Retrieved March 19, 2016, from http://www.flashmemorysummit.com/English/Collaterals/Proceedings/2009/20090811_F1A_Zajac.pdf.

[96]

Steve H. Weingart. 2000. Physical security devices for computer subsystems: A survey of attacks and defenses. In Cryptographic Hardware and Embedded Systems—CHES 2000. Springer, 302--317.

Digital Library

[97]

Wikipedia.org. 2010. CMOS Inverter Cross Section. Retrieved March 19, 2016, from http://en.wikipedia.org/wiki/CMOS.

[98]

Wikipedia.org. 2014. Printed Circuit+Board. Retrieved March 19, 2016, from http://en.wikipedia.org/wiki/Printed_circuit_board.

[99]

Thomas Wollinger, Jorge Guajardo, and Christof Paar. 2004. Security on FPGAs: State-of-the-art implementations and attacks. ACM Transactions on Embedded Computing Systems 3, 3, 534--574.

Digital Library

[100]

Wen-Yen Wu, Mao-Jiun J. Wang, and Chih-Ming Liu. 1996. Automated inspection of printed circuit boards through machine vision. Computers in Industry 28, 2, 103--111.

Digital Library

[101]

Jun Wu, Yong-Bin Kim, and Minsu Choi. 2010. Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. In Proceedings of the 20th Great Lakes Symposium on VLSI. ACM, New York, NY, 459--464.

Digital Library

[102]

Bulent Yener. 2014. CSCI 4974 / 6974 Hardware Reverse Engineering. Retrieved March 19, 2016, from http://security.cs.rpi.edu/courses/hwre-spring2014/.

[103]

Frank Zachariasse. 2012. Semiconductor device with backside tamper protection. US Patent 8,198,641.

[104]

Daniel Ziener, Stefan Assmus, and Jürgen Teich. 2006. Identifying FPGA IP-cores based on lookup table content analysis. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’06). IEEE, Los Alamitos, CA, 1--6.

Cited By

Zhan GZheng DHuang K(2024)A novel crosstalk based dynamic camouflage technique for preventing reverse engineeringIEICE Electronics Express10.1587/elex.21.20240165Online publication date: 2024
https://doi.org/10.1587/elex.21.20240165
Muttaki MRahman MKulkarni ATehranipoor MFarahmandi F(2024)FTC: A Universal Framework for Fault-Injection Attack Detection and PreventionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.338453132:7(1311-1324)Online publication date: Jul-2024
https://doi.org/10.1109/TVLSI.2024.3384531
Vega CSLPSK PBhunia S(2024)IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering AttacksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333731032:2(347-360)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2023.3337310
Show More Cited By

Index Terms

A Survey on Chip to System Reverse Engineering
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

Recommendations

ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks
Special Issue ESWEEK 2023
Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineering the NoC topology and routing ...
A Survey of Network-on-Chip Security Attacks and Countermeasures

With the advances of chip manufacturing technologies, computer architects have been able to integrate an increasing number of processors and other heterogeneous components on the same chip. Network-on-Chip (NoC) is widely employed by multicore System-on-...
Reverse engineering: a European IPR perspective
SAC '16: Proceedings of the 31st Annual ACM Symposium on Applied Computing

Even if reverse engineering is a well known and deeply investigated activity in software engineering, little research has been performed from an Intellectual Propriety Rights (IPRs) perspective. In this paper, we analyze some cases of reverse ...

Comments

Information & Contributors

Information

Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 13, Issue 1

Special Issue on Secure and Trustworthy Computing

January 2017

208 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/2917757

Editor:
Yuan Xie
University of California, Santa Barbara, USA

Issue’s Table of Contents

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 13 April 2016

Accepted: 01 April 2015

Revised: 01 March 2015

Received: 01 November 2014

Published in JETC Volume 13, Issue 1

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

177
Total Citations
View Citations
2,060
Total Downloads

Downloads (Last 12 months)211
Downloads (Last 6 weeks)15

Reflects downloads up to 11 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Zhan GZheng DHuang K(2024)A novel crosstalk based dynamic camouflage technique for preventing reverse engineeringIEICE Electronics Express10.1587/elex.21.20240165Online publication date: 2024
https://doi.org/10.1587/elex.21.20240165
Muttaki MRahman MKulkarni ATehranipoor MFarahmandi F(2024)FTC: A Universal Framework for Fault-Injection Attack Detection and PreventionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.338453132:7(1311-1324)Online publication date: Jul-2024
https://doi.org/10.1109/TVLSI.2024.3384531
Vega CSLPSK PBhunia S(2024)IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering AttacksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333731032:2(347-360)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2023.3337310
Ul Islam Sami MZamiri Azar KKamali HFarahmandi FTehranipoor M(2024)PQC-HI: PQC-enabled Chiplet Authentication and Key Exchange in Heterogeneous Integration2024 IEEE 74th Electronic Components and Technology Conference (ECTC)10.1109/ECTC51529.2024.00079(464-471)Online publication date: 28-May-2024
https://doi.org/10.1109/ECTC51529.2024.00079
Mildner MBrunner MGruber MBaehr JSigl G(2024)Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS60919.2024.10508905(53-56)Online publication date: 3-Apr-2024
https://doi.org/10.1109/DDECS60919.2024.10508905
Xiao WZhao FZhao KMa HLi Q(2024)TA-denseNet: Efficient hardware trust and assurance model based on feature extraction and comparison of SEM images and GDSII imagesIntegration10.1016/j.vlsi.2023.10211195(102111)Online publication date: Mar-2024
https://doi.org/10.1016/j.vlsi.2023.102111
Liu CWang KLi QZhao FZhao KMa H(2024)Novel methods for locating and matching IC cells based on standard cell librariesMicroelectronic Engineering10.1016/j.mee.2023.112107283:COnline publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1016/j.mee.2023.112107
Asadizanjani NXi CTehranipoor M(2024)Electron beam probing for advanced IC packaging assuranceMaterials for Electronics Security and Assurance10.1016/B978-0-44-318542-7.00019-1(183-198)Online publication date: 2024
https://doi.org/10.1016/B978-0-44-318542-7.00019-1
Asadizanjani NXi CTehranipoor M(2024)Sample preparation for hardware assuranceMaterials for Electronics Security and Assurance10.1016/B978-0-44-318542-7.00016-6(129-147)Online publication date: 2024
https://doi.org/10.1016/B978-0-44-318542-7.00016-6
Asadizanjani NXi CTehranipoor M(2024)Texture analysis of encapsulant packaging materialsMaterials for Electronics Security and Assurance10.1016/B978-0-44-318542-7.00013-0(81-103)Online publication date: 2024
https://doi.org/10.1016/B978-0-44-318542-7.00013-0
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents