Architecture and design of the HiPAR-DSP, a SIMD controlled signalprocessor with parallel data paths, VLIW and novel memory design.The processor architecture is derived from an analysis of thetarget algorithms and specified in VHDL on register transfer level.A team of more than 20 graduate students covered the whole designprocess, including the synthesizable VHDL description, synthesis,routing and backannotation as the development of a complete softwaredevelopment environment.The 175mm{2}, 0.5µm 3LM CMOSdesign with 1.2 million transistors operates at 80 MHz and achievesa sustained performance of more than 600 million arithmetic operations.

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Berekovic MNiggemeier T(2008)A distributed, simultaneously multi-threaded (SMT) processor with clustered scheduling windows for scalable DSP performanceJournal of Signal Processing Systems10.1007/s11265-007-0138-650:2(201-229)Online publication date: 1-Feb-2008
https://dl.acm.org/doi/10.1007/s11265-007-0138-6
Bereković MNiggemeier T(2006)A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo schemeProceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation10.1007/11796435_30(289-298)Online publication date: 17-Jul-2006
https://dl.acm.org/doi/10.1007/11796435_30
Liu XPapaefthymiou M(2003)Design of a 20-Mb/s 256-state viterbi decoderIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81754711:6(965-975)Online publication date: 1-Dec-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.817547
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Realization of a programmable parallel DSP for high performance image processing applications

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DAC '98: Proceedings of the 35th annual Design Automation Conference

May 1998

820 pages

ISBN:0897919645

DOI:10.1145/277044

Chairmen:
Basant R. Chawla
Lucent Technologies, Warren, NJ
,
Randal E. Bryant
Carnegie Mellon Univ., Pittsburgh, PA
,
Jan M. Rabaey
Univ. of California, Berkeley
,
Editor:
M. J. Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 May 1998

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Berekovic MNiggemeier T(2008)A distributed, simultaneously multi-threaded (SMT) processor with clustered scheduling windows for scalable DSP performanceJournal of Signal Processing Systems10.1007/s11265-007-0138-650:2(201-229)Online publication date: 1-Feb-2008
https://dl.acm.org/doi/10.1007/s11265-007-0138-6
Bereković MNiggemeier T(2006)A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo schemeProceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation10.1007/11796435_30(289-298)Online publication date: 17-Jul-2006
https://dl.acm.org/doi/10.1007/11796435_30
Liu XPapaefthymiou M(2003)Design of a 20-Mb/s 256-state viterbi decoderIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81754711:6(965-975)Online publication date: 1-Dec-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.817547
Liu XPapaefthymiou MAckland B(2002)Design of a high-throughput low-power IS95 Viterbi decoderProceedings of the 39th annual Design Automation Conference10.1145/513918.513988(263-268)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.513988
Xun Liu Papaefthymiou M(2002)Design of a high-throughput low-power IS95 Viterbi decoderProceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)10.1109/DAC.2002.1012633(263-268)Online publication date: 2002
https://doi.org/10.1109/DAC.2002.1012633
Berekovic MPirsch PSelinger TWels KMiro CLafage AHeer CGhigo G(2000)Co-processor architecture for MPEG-4 main profile visual compositing2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)10.1109/ISCAS.2000.856288(180-183)Online publication date: 2000
https://doi.org/10.1109/ISCAS.2000.856288
Berekovic MPirsch PSelinger TWels KMiro CLafage AHeer CGhigo G(2000)Architecture of an image rendering co-processor for MPEG-4 systemsProceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors10.1109/ASAP.2000.862374(15-24)Online publication date: 2000
https://doi.org/10.1109/ASAP.2000.862374
Berekovic MSelinger TMiro CGhigo GHeer CPirsch PWels KLafage A(1999)The TANGRAM co-processor for MPEG-4 visual compositing1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)10.1109/SIPS.1999.822336(311-320)Online publication date: 1999
https://doi.org/10.1109/SIPS.1999.822336

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