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Improving the Statistical Variability of Delay-based Physical Unclonable Functions

Published: 31 August 2015 Publication History

Abstract

Physical Unclonable Functions (PUFs) are circuits which exploit the statistical variability of the fabrication process to create a unique device identity. PUFs have been used in the design of cryptographic primitives for applications like device authentication, key generation and intellectual property protection. Due to its small cost and design simplicity, delay-based Arbiter PUFs (APUFs) have been considered a cryptographic engine candidate for the integration into low-cost IoT devices (e.g. RFID tags). Although APUFs have been extensively studied in the literature, not much work has been done in understanding how to improve its response variability using VLSI design techniques. This paper uses extensive AMS 350nm SPICE-based Monte-Carlo simulation to analyze how the proper selection of arbiter element and gate sizing can affect the delay variability of APUFs. Experimental results show that the combination of the appropriate arbiter and gate sizing configuration can considerably improve the Hamming Weight distribution of the APUF response, thus resulting in more reliable and less biased designs.

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Cited By

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  • (2021)A Lightweight Configurable XOR RO-PUF Design Based on Xilinx FPGA2021 IEEE 4th International Conference on Electronics Technology (ICET)10.1109/ICET51757.2021.9451016(83-88)Online publication date: 7-May-2021
  • (2021)A taxonomy of PUF Schemes with a novel Arbiter-based PUF resisting machine learning attacksComputer Networks10.1016/j.comnet.2021.108133194(108133)Online publication date: Jul-2021
  • (2019)High-Speed True Random Number Generator Based on Differential Current Starved Ring Oscillators with Improved Thermal Stability2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702785(1-5)Online publication date: May-2019
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cover image ACM Conferences
SBCCI '15: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design
August 2015
279 pages
ISBN:9781450337632
DOI:10.1145/2800986
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 31 August 2015

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Author Tags

  1. Monte-Carlo simulation
  2. Physical Unclonable Function (PUF)
  3. delay variability
  4. process variations

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  • Research-article
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  • Refereed limited

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SBCCI '15
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SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design
August 31 - September 4, 2015
Salvador, Brazil

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SBCCI '15 Paper Acceptance Rate 43 of 98 submissions, 44%;
Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

View all
  • (2021)A Lightweight Configurable XOR RO-PUF Design Based on Xilinx FPGA2021 IEEE 4th International Conference on Electronics Technology (ICET)10.1109/ICET51757.2021.9451016(83-88)Online publication date: 7-May-2021
  • (2021)A taxonomy of PUF Schemes with a novel Arbiter-based PUF resisting machine learning attacksComputer Networks10.1016/j.comnet.2021.108133194(108133)Online publication date: Jul-2021
  • (2019)High-Speed True Random Number Generator Based on Differential Current Starved Ring Oscillators with Improved Thermal Stability2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702785(1-5)Online publication date: May-2019
  • (2019)Theoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702722(1-5)Online publication date: May-2019
  • (2019)Low-Resource Hardware Architecture for Semi-Global Stereo Matching2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702234(1-4)Online publication date: May-2019
  • (2018)A low-overhead PUF based on parallel scan designProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201770(715-720)Online publication date: 22-Jan-2018
  • (2018)A low-overhead PUF based on parallel scan design2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297406(715-720)Online publication date: Jan-2018
  • (2017)Security enhancement of arbiter-based physical unclonable function on FPGAWuhan University Journal of Natural Sciences10.1007/s11859-017-1225-622:2(127-133)Online publication date: 11-Mar-2017
  • (2016)Memristor-based arbiter Physically Unclonable Function (APUF) with multiple response bits2016 IEEE Student Conference on Research and Development (SCOReD)10.1109/SCORED.2016.7810033(1-5)Online publication date: Dec-2016
  • (2016)Cylindrical Reconvergence Physical Unclonable Function2016 Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2016.100(446-453)Online publication date: Aug-2016

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