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The DASH prototype: implementation and performance

Published: 01 August 1998 Publication History
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References

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Agarwal, A., B.-H. Lira, D. Kranz, and J. Kubiamwicz. LimitLESS Directories: A Scalable Cache Coherence Scheme. In Pro(:. Fourth Int. Conf. on Architectural Support Programming Languages and Operating Systems. pp. 224- 234, 1991.
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Agarwal, A., R. Simoni, J. Hennessy, and M. Horowitz. An Evaluation of Directory Schemes for Cache Coherence. In Proc. 15th Int. Syrup. on Computer Architecture. pp. 280- 289, 1988.
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Baskett, F., T. jermoluk, and D. Solomon. The 4D-MP Graphics Superworkstation: Computing + Graphics = 40 MIPS + 40 MFLOPS and 100,000 Lighted Polygons per Second. In Proc. Compcon Spring 88. pp. 468-471, 1988.
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Censier, L. and P. Feautrier, A New Solution to Coherence Problems in Multicache Systems. IEEE Trans. on Computers, C(27): 1112-1118, 1978.
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Flaig, C.M., VLSI Mesh Routing Systems. Technical Report 5241:TR:87, California Institute of Technology, May 1987.
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Gupta, A., W.-D. Weber, and T. Mowry. Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes. In Proc. 1990 Int. Conf. on Parallel Processing. pp. I:312-321, 1990.
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Lenoski, D., 1. Laudon, K. Gharachorloo, A. Gupm, and J. Hennessy. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. In Proc. 17th Int. Syrup. on Computer Architecture. pp. 148-159, 1990.
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Lenoski, D., J. Laudon, K. Gharachorloo, W.-D. Weber, A. Gupta, J. Hennessy, M. Horowitz., and M. Lain, The Stanford DASH Multiprocessor. Computer, 250), 1992.
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Lenoski, D.E., The Design and Analysis of DASH : A Scalable Directory-Based Multiprocessor. Ph.D. Thesis. Stanford University. 1991. Also available as Stanford University Technical Report CSL-TR-92-507
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Papamarcos, M.S. and J.H. Patel. A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories. In Proc. I I th Int. Syrup. on Computer Architecture. pp. 348-354, 1984.
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Singh, J.P.,C. Holt, T.Totsuka, A.Gupta, andJ.L. Hennessy, Load Balancing and Data l.,ocality in Parallel N-body Techniques. Technical Report CSL-TR-92-505, Stanford University, 199 I.
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Singh, J.P., W.-D. Weber, and A. Gupta, SPLASH: Stanford Parallel Applications for Shared Memory. Technical Report CSL-TR-91-469, Stanford University, 1991.
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  • (2008)A consistency architecture for hierarchical shared cachesProceedings of the twentieth annual symposium on Parallelism in algorithms and architectures10.1145/1378533.1378536(11-22)Online publication date: 1-Jun-2008

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cover image ACM Conferences
ISCA '98: 25 years of the international symposia on Computer architecture (selected papers)
August 1998
546 pages
ISBN:1581130589
DOI:10.1145/285930
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  • (2024)NotNets: Accelerating Microservices by Bypassing the NetworkProceedings of the 15th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3678015.3680494(67-73)Online publication date: 4-Sep-2024
  • (2008)A consistency architecture for hierarchical shared cachesProceedings of the twentieth annual symposium on Parallelism in algorithms and architectures10.1145/1378533.1378536(11-22)Online publication date: 1-Jun-2008

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