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Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead

Published: 28 March 2016 Publication History
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  • Abstract

    This work proposes a novel scheme to facilitate heterogeneous systems with unified virtual memory. Research proposals implement coherence protocols for sequential consistency (SC) between central processing unit (CPU) cores and between devices. Such mechanisms introduce severe bottlenecks in the system; therefore, we adopt the heterogeneous-race-free (HRF) memory model. The use of HRF simplifies the coherency protocol and the graphics processing unit (GPU) memory management unit (MMU). Our protocol optimizes CPU and GPU demands separately, with the GPU part being simpler while the CPU is more elaborate and latency aware. We achieve an average 45% speedup and 45% energy-delay product reduction (20% energy) over the corresponding SC implementation.

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    Cited By

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    • (2023)Improving the Scalability of GPU Synchronization PrimitivesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.321850834:1(275-290)Online publication date: 1-Jan-2023
    • (2022)Demystifying BERT: System Design Implications2022 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC55918.2022.00033(296-309)Online publication date: Nov-2022
    • (2022)HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00061(756-771)Online publication date: Apr-2022
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    1. Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead

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      Published In

      cover image ACM Transactions on Architecture and Code Optimization
      ACM Transactions on Architecture and Code Optimization  Volume 13, Issue 1
      April 2016
      347 pages
      ISSN:1544-3566
      EISSN:1544-3973
      DOI:10.1145/2899032
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 28 March 2016
      Accepted: 01 November 2015
      Revised: 01 October 2015
      Received: 01 May 2015
      Published in TACO Volume 13, Issue 1

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      Author Tags

      1. GPU MMU design
      2. Multicore
      3. directory-less protocol
      4. heterogeneous coherence
      5. virtual coherence protocol

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      • Research-article
      • Research
      • Refereed

      Funding Sources

      • Swedish Research Council UPMARC Linnaeus Centre
      • European Commission FEDER funds
      • “Fundación Seneca-Agencia de Ciencia y Tecnología de la Región de Murcia”
      • the Spanish MINECO
      • EU Project LPGPU
      • the project “Jóvenes Líderes en Investigación”

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      Cited By

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      • (2023)Improving the Scalability of GPU Synchronization PrimitivesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.321850834:1(275-290)Online publication date: 1-Jan-2023
      • (2022)Demystifying BERT: System Design Implications2022 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC55918.2022.00033(296-309)Online publication date: Nov-2022
      • (2022)HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00061(756-771)Online publication date: Apr-2022
      • (2022)Only Buffer When You Need To: Reducing On-chip GPU Traffic with Reconfigurable Local Atomic Buffers2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00056(676-691)Online publication date: Apr-2022
      • (2020)Inter-kernel Reuse-aware Thread Block SchedulingACM Transactions on Architecture and Code Optimization10.1145/340653817:3(1-27)Online publication date: 17-Aug-2020
      • (2020)Deterministic Atomic Buffering2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00083(981-995)Online publication date: Oct-2020
      • (2020)HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00054(582-595)Online publication date: Feb-2020
      • (2019)Compiler assisted hybrid implicit and explicit GPU memory management under unified address spaceProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3295500.3356141(1-16)Online publication date: 17-Nov-2019
      • (2018)Filtering Translation Bandwidth with Virtual CachingACM SIGPLAN Notices10.1145/3296957.317319553:2(113-127)Online publication date: 19-Mar-2018
      • (2018)Filtering Translation Bandwidth with Virtual CachingProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173195(113-127)Online publication date: 19-Mar-2018
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