research-article

Practical statistical static timing analysis with current source models

Authors:

Vladimir Zolotov,

Sheshashayee K. Raghunathan,

Michael H. Wood,

Kerim KalafalaAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 113, Pages 1 - 6

https://doi.org/10.1145/2897937.2898068

Published: 05 June 2016 Publication History

Abstract

This paper considers the practical nuances of using current source gate models in an industrial statistical timing analysis environment. Specifically, the memory overhead of a naive implementation combining statistical and current source models to obtain and store gate output waveforms is found to be impractical for large microprocessor designs. A study is performed to observe variational gate output waveforms, and a technique is presented to store the waveforms in a memory efficient manner with minimal accuracy impact. The presented technique is validated over a set of 14 nanometer designs, and has enabled the usage of current source models in our industrial statistical timing analysis flow. Results demonstrate slack accuracy improvements of up to 17 picoseconds with a 1.15X run-time overhead and 1.1 gigabytes per million-gates memory overhead in comparison to an existing flow.

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Cited By

Abrishami MGe HCalderon JPedram MNazarian S(2020)NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework2020 21st International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED48828.2020.9137047(452-456)Online publication date: Mar-2020
https://doi.org/10.1109/ISQED48828.2020.9137047
Abrishami MPedram MNazarian S(2019)CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00061(393-400)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00061

Index Terms

Practical statistical static timing analysis with current source models
1. Hardware
  1. Hardware validation

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cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

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Published: 05 June 2016

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Abrishami MGe HCalderon JPedram MNazarian S(2020)NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework2020 21st International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED48828.2020.9137047(452-456)Online publication date: Mar-2020
https://doi.org/10.1109/ISQED48828.2020.9137047
Abrishami MPedram MNazarian S(2019)CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00061(393-400)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00061

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