short-paper

Load Balanced On-Chip Power Delivery for Average Current Demand

Authors:

Divya Pathak,

Mohammad Hossein Hajkazemi,

Mohammad Khavari Tavana,

Houman Homayoun,

Ioannis SavidisAuthors Info & Claims

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

Pages 439 - 444

https://doi.org/10.1145/2902961.2903030

Published: 18 May 2016 Publication History

Get Access

Abstract

A dynamic power management system for homogeneous chip multi-processors (CMP) is proposed. Each core of the CMP includes on chip DC-DC switching buck converters that are interconnected through a switch network. The peak current rating of the buck converter is selected to meet only the average current demand of the load circuit. A real-time load balancing algorithm is developed which reconfigures the power delivery network by combining the output of multiple buck converters when the workload demand exceeds the peak current rating. Simulation results for the proposed power delivery method indicate up to a 44% reduction in the energy consumption of the CMP system. In addition, the on-chip footprint of the power delivery network, including the on-chip voltage regulators and the switching network, is reduced by at least 23%.

References

[1]

W. Kim et al, "System Level Analysis of Fast, Per-Core DVFS Using On-chip Switching Regulators," Proceedings of the International Symposium on High Performance Computer Architecture, pp. 123--134, February 2008.

Google Scholar

[2]

E.A. Burton et al, "FIVR-Fully Integrated Voltage Regulators on 4th Generation Intel Core SoCs," IEEE Applied Power Electronics Conference and Exposition, pp. 432--439, March 2014.

Google Scholar

[3]

E.J. Fluhr et al, "The 12-Core POWER Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking," IEEE Journal of Solid-State Circuits, Vol. 50, No. 1, pp. 10--23, January 2015.

Crossref

Google Scholar

[4]

mersenne.org, "Great Internet Mersenne Prime Search," http://www.mersenne.org/download/#stresstest.

Google Scholar

[5]

S. Li et al, "McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures," IEEE/ACM International Symposium on Microarchitecture, pp. 469--480, 2009.

Digital Library

Google Scholar

[6]

W. Godycki et al, \Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks," Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 381--393, December 2014.

Digital Library

Google Scholar

[7]

W. Lee et al, "Optimizing a Reconfigurable Power Distribution Network in a Multicore Platform," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 7, pp. 1110--1123, July 2015.

Crossref

Google Scholar

[8]

M. Sai et al, "3D Many-core Microprocessor Power Management by Space-Time Multiplexing based Demand-supply Matching," IEEE Transaction on Computers, Vol. 64, No. 11, pp. 3022--3036, November 2015.

Digital Library

Google Scholar

[9]

I. Vaisband and E.G. Friedman, "Energy efficient adaptive clustering of on-chip power delivery systems," INTEGRATION, The VLSI Journal, Vol. 48, pp. 1--9, January 2015.

Digital Library

Google Scholar

[10]

M. Tavana et al, "Realizing Complixity-Effective On-Chip Power Delivery for Many-Core Platforms by Exploiting Optimized Mapping," Proceedings of the International Conference on Computer Design, pp. 581--588, October 2015.

Digital Library

Google Scholar

[11]

D.M. Tullsen, \Simulation and Modeling of a Simultaneous Multithreading Processor," Proceedings of the International Conference for the Resource Management & Performance Evaluation of Enterprise Computing Systems, CMG. Part 2(of 2), pp. 819--828, 1996.

Google Scholar

[12]

E. Salman and E.G. Friedman, High Performance Integrated Circuit Design, McGraw Hill, 2012.

Google Scholar

[13]

Texas Instruments, "WEBENCH Design Center," http://webench.ti.com.

Google Scholar

Cited By

View all

Li HTian ZXu JMaeda RWang ZWang Z(2020)Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement LearningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.296686628:5(1150-1163)Online publication date: May-2020
https://doi.org/10.1109/TVLSI.2020.2966866
Pathak DHomayoun HSavidis IBehjat LHan JVelev MChen D(2017)Work Load Scheduling For Multi Core Systems With Under-Provisioned Power DeliveryProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060498(387-392)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060498
Pathak DHomayoun HSavidis I(2017)Smart Grid on Chip: Work Load-Balanced On-Chip Power DeliveryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.269964425:9(2538-2551)Online publication date: Sep-2017
https://doi.org/10.1109/TVLSI.2017.2699644

Index Terms

Load Balanced On-Chip Power Delivery for Average Current Demand
1. Hardware
  1. Power and energy
    1. Energy distribution
      1. Power conversion
    2. Power estimation and optimization
      1. Chip-level power issues
      2. Circuits power issues
  2. Very large scale integration design
    1. On-chip resource management

Recommendations

Active filter-based hybrid on-chip DC-DC converter for point-of-load voltage regulation

An active filter-based on-chip DC-DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the ...
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
DAC '10: Proceedings of the 47th Design Automation Conference

Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates system-level power management. The quantitative understanding of such complex power ...
A Novel On-Chip Amplifier for Fast I_DD Current Monitoring

A novel circuit of the low-voltage application-specific amplifier is proposed and analyzed. A wide-band current amplifying cell is developed as a central part of the amplifier structure. The amplifier is designed for a built-in-current-sensor, on-chip ...

Comments

Information & Contributors

Information

Published In

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

May 2016

462 pages

ISBN:9781450342742

DOI:10.1145/2902961

General Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA
,
Program Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 May 2016

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Short-paper

Conference

GLSVLSI '16

Sponsor:

SIGDA

GLSVLSI '16: Great Lakes Symposium on VLSI 2016

May 18 - 20, 2016

Massachusetts, Boston, USA

Acceptance Rates

GLSVLSI '16 Paper Acceptance Rate 50 of 197 submissions, 25%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Upcoming Conference

GLSVLSI '25

Sponsor:
sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
77
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Li HTian ZXu JMaeda RWang ZWang Z(2020)Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement LearningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.296686628:5(1150-1163)Online publication date: May-2020
https://doi.org/10.1109/TVLSI.2020.2966866
Pathak DHomayoun HSavidis IBehjat LHan JVelev MChen D(2017)Work Load Scheduling For Multi Core Systems With Under-Provisioned Power DeliveryProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060498(387-392)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060498
Pathak DHomayoun HSavidis I(2017)Smart Grid on Chip: Work Load-Balanced On-Chip Power DeliveryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.269964425:9(2538-2551)Online publication date: Sep-2017
https://doi.org/10.1109/TVLSI.2017.2699644

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Cited By

Index Terms

Recommendations

Active filter-based hybrid on-chip DC-DC converter for point-of-load voltage regulation

Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation

A Novel On-Chip Amplifier for Fast I_DD Current Monitoring

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Active filter-based hybrid on-chip DC-DC converter for point-of-load voltage regulation

Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation

A Novel On-Chip Amplifier for Fast IDD Current Monitoring

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations

A Novel On-Chip Amplifier for Fast I_DD Current Monitoring