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View all- Zamarrud Izharuddin M(2018)8-Bit Quantizer for Chaotic Generator With Reduced Hardware ComplexityInternational Journal of Rough Sets and Data Analysis10.4018/IJRSDA.20180701045:3(55-70)Online publication date: 1-Jul-2018
Chaotic encryption schemes are believed to provide greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details over Xilinx Virtex-6 FPGA are provided. ...
In this study, autonomous Lü-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math fixed-point number format for developing embedded chaos-based engineering applications. The core ...
In this paper we describe Xilinx's Versal-Adaptive Compute Acceleration Platform (ACAP). ACAP is a hybrid compute platform that tightly integrates traditional FPGA programmable fabric, software programmable processors and software programmable ...
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