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A design to reduce write amplification in object-based NAND flash devices

Published: 01 October 2016 Publication History

Abstract

Write amplification is a major cause of performance and endurance degradations in NAND flash based storage systems. In an object-based NAND flash device, two causes of write amplification are onode partial update and cascading update. Updating one onode, a kind of small-sized object metadata, invokes partial page update (i.e., onode partial update) that incurs unnecessary migration of the un-updated data. An cascading update denotes that object metadata is updated in a cascading manner due to erase-before-program property of NAND flash memory. In this work, we propose a system design to alleviate onode partial update and cascading update. The proposed system design includes: 1) A multi-level garbage collection technique to minimize unnecessary data migration incurred by onode partial update; 2) A B+ table tree and selective cache design to reduce the write operations associated with cascading update; and 3) A power failure handling technique to guarantee system consistency. Experiment results show that our proposed design can achieve up to 20% write reduction compared to the best state-of-the-art.

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  • (2019)A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.280822738:2(234-244)Online publication date: Feb-2019
  • (2018)ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342206(1247-1252)Online publication date: Mar-2018
  • (2018)DLSpaceACM Transactions on Embedded Computing Systems10.1145/328474917:6(1-33)Online publication date: 8-Dec-2018
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    cover image ACM Other conferences
    CODES '16: Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
    October 2016
    294 pages
    ISBN:9781450344838
    DOI:10.1145/2968456
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 01 October 2016

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    Author Tags

    1. NAND flash memories
    2. write amplification

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    ESWEEK'16
    ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK
    October 1 - 7, 2016
    Pennsylvania, Pittsburgh

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    View all
    • (2019)A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.280822738:2(234-244)Online publication date: Feb-2019
    • (2018)ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342206(1247-1252)Online publication date: Mar-2018
    • (2018)DLSpaceACM Transactions on Embedded Computing Systems10.1145/328474917:6(1-33)Online publication date: 8-Dec-2018
    • (2017)P-AllocACM Transactions on Embedded Computing Systems10.1145/312655416:5s(1-19)Online publication date: 27-Sep-2017
    • (2017)FlashKVACM Transactions on Embedded Computing Systems10.1145/312654516:5s(1-19)Online publication date: 27-Sep-2017
    • (2017)Improving Write Performance and Extending Endurance of Object-Based NAND Flash DevicesACM Transactions on Embedded Computing Systems10.1145/310592417:1(1-26)Online publication date: 14-Nov-2017
    • (2017)Data-Pattern-Aware Error Prevention Technique to Improve System ReliabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.264205525:4(1433-1443)Online publication date: 1-Apr-2017
    • (2017)FlexLevel NAND Flash Storage System Design to Reduce LDPC LatencyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261948036:7(1167-1180)Online publication date: Jul-2017
    • (2017)Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858416(764-769)Online publication date: Jan-2017

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