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Trace-based Register Allocation in a JIT Compiler

Published: 29 August 2016 Publication History

Abstract

State-of-the-art dynamic compilers often use global approaches, like Linear Scan or Graph Coloring, for register allocation. These algorithms consider the complete compilation unit for allocation, which increases the complexity of the implementation (e.g., support for lifetime holes in Linear Scan) and potentially also affects compilation time. We propose a novel non-global algorithm, which splits a compilation unit into traces based on profiling feedback and subsequently performs register allocation within each trace individually. Traces reduce the problem size to a single linear code segment, which simplifies the problem a register allocator needs to solve. Additionally, we can apply different register allocation algorithms to each trace. We show that this non-global approach can achieve results competitive to global register allocation.
We present an implementation of Trace Register Allocation based on the Graal VM and show an evaluation for common Java benchmarks. We demonstrate that performance of this non-global approach is within 3% (on AMD64) and 1% (on SPARC) of global Linear Scan register allocation.

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  1. Trace-based Register Allocation in a JIT Compiler

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    cover image ACM Other conferences
    PPPJ '16: Proceedings of the 13th International Conference on Principles and Practices of Programming on the Java Platform: Virtual Machines, Languages, and Tools
    August 2016
    186 pages
    ISBN:9781450341356
    DOI:10.1145/2972206
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 29 August 2016

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    Author Tags

    1. Just-in-Time Compilation
    2. Linear Scan
    3. Register Allocation
    4. Trace Compilation
    5. Trace Register Allocation
    6. Virtual Machines

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    PPPJ '16
    PPPJ '16: Virtual Machines, Languages, and Tools
    August 29 - September 2, 2016
    Lugano, Switzerland

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    PPPJ '16 Paper Acceptance Rate 14 of 31 submissions, 45%;
    Overall Acceptance Rate 29 of 58 submissions, 50%

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    Cited By

    View all
    • (2023)Exploiting Partially Context-sensitive Profiles to Improve Performance of Hot CodeACM Transactions on Programming Languages and Systems10.1145/361293745:4(1-64)Online publication date: 13-Sep-2023
    • (2020)Irregular Register Allocation for Translation of Test-pattern ProgramsACM Transactions on Architecture and Code Optimization10.1145/342737818:1(1-23)Online publication date: 30-Dec-2020
    • (2019)Practical second Futamura projection: partial evaluation for high-performance language interpretersProceedings Companion of the 2019 ACM SIGPLAN International Conference on Systems, Programming, Languages, and Applications: Software for Humanity10.1145/3359061.3361077(29-31)Online publication date: 20-Oct-2019
    • (2019)Renaissance: benchmarking suite for parallel applications on the JVMProceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3314221.3314637(31-47)Online publication date: 8-Jun-2019
    • (2019)QuickCheck: using speculation to reduce the overhead of checks in NVM frameworksProceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments10.1145/3313808.3313822(137-151)Online publication date: 14-Apr-2019
    • (2018)A cost model for a graph-based intermediate-representation in a dynamic compilerProceedings of the 10th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages10.1145/3281287.3281290(26-35)Online publication date: 4-Nov-2018
    • (2018)Parallel trace register allocationProceedings of the 15th International Conference on Managed Languages & Runtimes10.1145/3237009.3237010(1-7)Online publication date: 12-Sep-2018
    • (2017)Trace Register Allocation PoliciesProceedings of the 14th International Conference on Managed Languages and Runtimes10.1145/3132190.3132209(92-104)Online publication date: 27-Sep-2017

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