research-article

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System

Authors:

Vaughn Betz, and

Jonathan RoseAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 10, Issue 1

Article No.: 7, Pages 1 - 22

https://doi.org/10.1145/2974022

Published: 09 December 2016 Publication History

Abstract

Although FPGAs have grown in capacity, FPGA-based soft processors have grown very little because of the difficulty of achieving higher performance in exchange for area. Superscalar out-of-order processors promise large performance gains, and the memory subsystem is a key part of such a processor that must help supply increased performance. In this article, we describe and explore microarchitectural and circuit-level tradeoffs in the design of such a memory system. We show the significant instructions-per-cycle wins for providing various levels of out-of-order memory access and memory dependence speculation (1.32 × SPECint2000) and for the addition of a second-level cache (another 1.60 × ). With careful microarchitecture and circuit design, we also achieve a L1 translation lookaside buffers and cache lookup with 29% less logic delay than the simpler Nios II/f memory system.

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Alipour MKaxiras SBlack-Schaffer DKumar R(2020)Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00042(424-434)Online publication date: Feb-2020
https://doi.org/10.1109/HPCA47549.2020.00042
Matthews EGao YShannon L(2020)Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM48280.2020.00025(120-128)Online publication date: May-2020
https://doi.org/10.1109/FCCM48280.2020.00025
Show More Cited By

Index Terms

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System
1. Computer systems organization
  1. Architectures
    1. Serial architectures
      1. Superscalar architectures
2. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Sequential circuits
    2. Reconfigurable logic and FPGAs
      1. Reconfigurable logic applications

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 10, Issue 1

March 2017

206 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3002131

Editor:
Steve Wilton
Department of Electrical and Computer Engineering / University of British Columbia / Kaiser 4112, 5500-2332 Main Mall / Vancouver, BC V6T 1Z4 Canada

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Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 December 2016

Accepted: 01 July 2016

Revised: 01 June 2016

Received: 01 February 2016

Published in TRETS Volume 10, Issue 1

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Alipour MKaxiras SBlack-Schaffer DKumar R(2020)Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00042(424-434)Online publication date: Feb-2020
https://doi.org/10.1109/HPCA47549.2020.00042
Matthews EGao YShannon L(2020)Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM48280.2020.00025(120-128)Online publication date: May-2020
https://doi.org/10.1109/FCCM48280.2020.00025
Mashimo SInoue KShioya RFujita AMatsuo RAkaki SFukuda AKoizumi TKadomoto JIrie HGoshima M(2019)An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00016(63-71)Online publication date: Dec-2019
https://doi.org/10.1109/ICFPT47387.2019.00016
Matthews EAguila ZShannon L(2018)Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2018.00010(1-8)Online publication date: Apr-2018
https://doi.org/10.1109/FCCM.2018.00010

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