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Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

Authors:

Jiang Hu,

Sachin S. SapatnekarAuthors Info & Claims

ISPD '99: Proceedings of the 1999 international symposium on Physical design

Pages 133 - 138

https://doi.org/10.1145/299996.300041

Published: 12 April 1999 Publication History

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Cited By

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Liang RXie ZBarboza EHu J(2022)Net-Based Machine Learning-Aided Approaches for Timing and Crosstalk PredictionMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_3(63-84)Online publication date: 10-Aug-2022
https://doi.org/10.1007/978-3-031-13074-8_3
Zhang YChakraborty AChowdhury SPan DHu A(2012)Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree constructionProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429410(137-143)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429410
Cong JKoh CMadden P(2006)Interconnect layout optimization under higher order RLC model for MCM designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.96943820:12(1455-1463)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.969438
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Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

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In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable ...

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ISPD '99: Proceedings of the 1999 international symposium on Physical design

April 1999

223 pages

ISBN:1581130899

DOI:10.1145/299996

Chairman:
D. F. Wong
Univ. of Texas-Austin

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Published: 12 April 1999

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April 12 - 14, 1999

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Liang RXie ZBarboza EHu J(2022)Net-Based Machine Learning-Aided Approaches for Timing and Crosstalk PredictionMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_3(63-84)Online publication date: 10-Aug-2022
https://doi.org/10.1007/978-3-031-13074-8_3
Zhang YChakraborty AChowdhury SPan DHu A(2012)Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree constructionProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429410(137-143)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429410
Cong JKoh CMadden P(2006)Interconnect layout optimization under higher order RLC model for MCM designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.96943820:12(1455-1463)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.969438
Alpert CGandham GHu JNeves JQuay SSapatnekar S(2006)Steiner tree optimization for buffers, blockages, and baysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.91821320:4(556-562)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.918213
Khandelwal VDavoodi ANanavati ASrivastava A(2003)A Probabilistic Approach to Buffer InsertionProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009945Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009945
Khandelwal VDavoodi ANanavati ASrivastava A(2003)A probabilistic approach to buffer insertionICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)10.1109/ICCAD.2003.159738(560-567)Online publication date: 2003
https://doi.org/10.1109/ICCAD.2003.159738
Coudert O(2002)Timing and design closure in physical design flowsProceedings International Symposium on Quality Electronic Design10.1109/ISQED.2002.996796(511-516)Online publication date: 2002
https://doi.org/10.1109/ISQED.2002.996796
Coudert O(2002)Logical and Physical Design: A Flow PerspectiveLogic Synthesis and Verification10.1007/978-1-4615-0817-5_7(167-196)Online publication date: 2002
https://doi.org/10.1007/978-1-4615-0817-5_7
Coudert O(2001)Logical and physical designLogic Synthesis and Verification10.5555/566845.566852(167-196)Online publication date: 1-Nov-2001
https://dl.acm.org/doi/10.5555/566845.566852
Alpert CGandham GHu JNeves JQuay SSapatnekar S(2001)Steiner tree optimization for buffers. Blockages and baysISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)10.1109/ISCAS.2001.922069(399-402)Online publication date: 2001
https://doi.org/10.1109/ISCAS.2001.922069
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Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model

An improved RC model for VLSI interconnects with applications to buffer insertion

A new approach to simultaneous buffer insertion and wire sizing

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Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model

An improved RC model for VLSI interconnects with applications to buffer insertion

A new approach to simultaneous buffer insertion and wire sizing

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