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Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems

Authors:

Jawad Haj-Yihia,

Ahmad Yasin,

Yosi Ben Asher,

Avi MendelsonAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 13, Issue 4

Article No.: 56, Pages 1 - 25

https://doi.org/10.1145/3018112

Published: 16 December 2016 Publication History

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Abstract

A detailed analysis of power consumption at low system levels becomes important as a means for reducing the overall power consumption of a system and its thermal hot spots. This work presents a new power estimation method that allows understanding the power breakdown of an application when running on modern processor architecture such as the newly released Intel Skylake processor. This work also provides a detailed power and performance characterization report for the SPEC CPU2006 benchmarks, analysis of the data using side-by-side power and performance breakdowns, as well as few interesting case studies.

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Cited By

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Qi XChen JDeng RLi ZDeng LYuan YChe Y(2024)PowerDis: Fine-Grained Power Monitoring Through Power Disaggregation ModelAlgorithms and Architectures for Parallel Processing10.1007/978-981-97-0859-8_20(325-346)Online publication date: 27-Feb-2024
https://doi.org/10.1007/978-981-97-0859-8_20
Ravipati Dvan Santen VSalamin SAmrouch HPanda P(2023)Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPATIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.328510531:9(1280-1293)Online publication date: 1-Sep-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3285105
Umeike JPatel NManley AMamandipoor AYun HAlian M(2023)Profiling gem5 Simulator2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS57527.2023.00019(103-113)Online publication date: May-2023
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Index Terms

Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems
1. Computing methodologies
  1. Modeling and simulation
2. Hardware
  1. Power and energy
    1. Power estimation and optimization

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Reviews

Reviewer: Karthik S Murthy

Extreme-scale data centers and supercomputers draw many megawatts of power to function. By today's standards, drawing one megawatt of power roughly costs $1 million; hence, reduced power consumption is critical for these systems. Current and upcoming systems are very efficient in terms of power usage effectiveness (PUE); for example, Intel home-built data centers run at 1.06 PUE and Facebook's centers run at 1.078 PUE. These PUE numbers tell us that most of the power drawn on these systems is used for application execution, and therefore developers need to shoulder the responsibility of achieving power efficiency as well. Rotem et al. [1] show that detailed power modeling is necessary because it is not straightforward to gauge whether (1) running a processor at a high frequency to complete the application faster and then putting the processor to sleep or (2) running a processor at a low frequency for a longer time to execute the application results in an efficient power envelope. This paper develops a tool that provides a fine-grained breakdown of the power consumed by different processor and sub-processor domains on the Intel Skylake system. Intel VTune helps identify performance bottlenecks by employing the top-down analysis method developed by Ahmad Yasin in 2014 [2]. Top-down analysis is built on the idea that studying performance counters in isolation is not as informative as studying them in groups. These (sub)groups of performance counters, that is, meta-performance counters, are useful in pinpointing whether the performance bottlenecks in the developer's application are frontend-bound or backend-bound or whether they have occurred due to misspeculations. Similarly, the tool built by the authors helps classify whether the power consumption in an application is frontend-bound, backend-bound, or due to misspeculation. To build these meta-performance counters, the authors had to identify weights for each of the performance counters, which make up a meta-performance counter. To do so, they used a set of training microbenchmarks. Overall, the paper is very informative and nicely written. The experiments are substantial. However, as the authors admit, these counters were studied for one core and one p-state, which is hardly the case in the wild. Online Computing Reviews Service

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 13, Issue 4

December 2016

648 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/3012405

Editor:
Koen De Bosschere
Ghent University

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 16 December 2016

Accepted: 01 November 2016

Revised: 01 October 2016

Received: 01 June 2016

Published in TACO Volume 13, Issue 4

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Power consumption and reduction in a real, commercial multimedia core

Dynamic MIPS Rate Stabilization for Complex Processors

An experimental evaluation of real-time DVFS scheduling algorithms

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