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An Efficient Performance-Driven Approach for HW/SW Co-Design

Published: 17 April 2017 Publication History
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  • Abstract

    Nowadays embedded systems are powerful and everywhere. They implement complex functionality relying on a huge set of different hardware and software (HW/SW) architectures. In order to reduce their development effort, HW/SW Co-Design techniques are used during the entire development cycle. These techniques aim at helping designers to define a feasible hardware and software partitioning for the system in such a way that functional and non-functional requirements are fulfilled. In this context Design Space Exploration is a challenging activity since a huge number of different implementation alternatives need to be evaluated.
    By exploiting some intrinsic properties of the embedded system domain, in this paper we propose our vision for a novel Performance-Driven HW/SW Co-Design methodology. It combines: (i) the "design for verifiability" concept, suitable to model the system behavior avoiding the state space explosion problem, and (ii) model-driven techniques to address performance issues. For this goal, we introduce the concepts underlying: (i) a novel formal modeling language and, (ii) a performance-driven verification/transformation chain.

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    Cited By

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    • (2020)An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the “Design for Monitorability” Project - Work-in-Progress2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)10.1109/CODESISSS51650.2020.9244025(40-42)Online publication date: 20-Sep-2020
    • (2019)Tuning DSE for Heterogeneous Multi-Processor Embedded Systems by means of a Self-Equalized Weighted Sum MethodProceedings of the 10th and 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms10.1145/3310411.3310412(1-4)Online publication date: 21-Jan-2019
    • (2018)CC4CSCompanion of the 2018 ACM/SPEC International Conference on Performance Engineering10.1145/3185768.3186291(119-122)Online publication date: 2-Apr-2018
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    cover image ACM Conferences
    ICPE '17: Proceedings of the 8th ACM/SPEC on International Conference on Performance Engineering
    April 2017
    450 pages
    ISBN:9781450344043
    DOI:10.1145/3030207
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 17 April 2017

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    Author Tags

    1. design for verifiability
    2. hw/sw co-design
    3. model-driven engineering
    4. performance awareness

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    ICPE '17 Paper Acceptance Rate 27 of 83 submissions, 33%;
    Overall Acceptance Rate 252 of 851 submissions, 30%

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    View all
    • (2020)An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the “Design for Monitorability” Project - Work-in-Progress2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)10.1109/CODESISSS51650.2020.9244025(40-42)Online publication date: 20-Sep-2020
    • (2019)Tuning DSE for Heterogeneous Multi-Processor Embedded Systems by means of a Self-Equalized Weighted Sum MethodProceedings of the 10th and 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms10.1145/3310411.3310412(1-4)Online publication date: 21-Jan-2019
    • (2018)CC4CSCompanion of the 2018 ACM/SPEC International Conference on Performance Engineering10.1145/3185768.3186291(119-122)Online publication date: 2-Apr-2018
    • (2018)Criticality-aware Design Space Exploration for Mixed-Criticality Embedded SystemsCompanion of the 2018 ACM/SPEC International Conference on Performance Engineering10.1145/3185768.3185769(45-46)Online publication date: 2-Apr-2018
    • (2018)Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded SystemsProceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms10.1145/3183767.3183782(63-68)Online publication date: 23-Jan-2018
    • (2018)HEPSYCODE-RTProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180670(1-6)Online publication date: 22-Jan-2018
    • (2018)HEPSIM: An ESL HW/SW co-simulator/analysis tool for heterogeneous parallel embedded systems2018 7th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2018.8406078(1-6)Online publication date: Jun-2018
    • (2018)Injecting hypervisor-based software partitions into Design Space Exploration activities considering mixed-criticality requirements2018 7th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2018.8406056(1-5)Online publication date: Jun-2018
    • (2018)Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions2018 21st Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2018.00115(740-744)Online publication date: Aug-2018

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