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Cache design of a sub-micron CMOS system/370

Authors:

J. H. Chang,

H. Chao,

K. SoAuthors Info & Claims

ISCA '87: Proceedings of the 14th annual international symposium on Computer architecture

Pages 208 - 213

https://doi.org/10.1145/30350.30374

Published: 01 June 1987 Publication History

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Abstract

An innovative cache accessing scheme based on high MRU (most recently used) hit ratio [1] is proposed for the design of a one-cycle cache in a CMOS implementation of System/370. It is shown that with this scheme the cache access time is reduced by 30 ~ 35% and the performance is within 4% of a true one-cycle cache. This cache scheme is proposed to be used in a VLSI System/370, which is organized to achieve high performance by taking advantage of the performance and integration level of an advanced CMOS technology with half-micron channel length [2]. Decisions on the system partition are based on technology limitations, performance considerations and future extendability. Design decisions on various aspects of the cache organization are based on trace simulations for both UP (uniprocessor) and MP (multiprocessor) configurations.

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Cited By

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Chen H(2011)Low-power way-predicting cache based on intrablock accessJournal of the Chinese Institute of Engineers10.1080/02533839.2011.57650034:4(529-537)Online publication date: Jun-2011
https://doi.org/10.1080/02533839.2011.576500
Kannan MDeepu KIype JParthasarathy RGautham P(2010)Power Consumption Analysis of Direct, Set Associative and Phased Set Associative Cache Organizations in Alpha AXP 21064 ProcessorInformation Processing and Management10.1007/978-3-642-12214-9_20(114-119)Online publication date: 2010
https://doi.org/10.1007/978-3-642-12214-9_20
Megalingam RDeepu KJoseph IVikram V(2009)Phased set associative cache design for reduced power consumption2009 2nd IEEE International Conference on Computer Science and Information Technology10.1109/ICCSIT.2009.5234663(551-556)Online publication date: Aug-2009
https://doi.org/10.1109/ICCSIT.2009.5234663
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Index Terms

Cache design of a sub-micron CMOS system/370
1. General and reference
  1. Cross-computing tools and techniques
    1. Design
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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ISCA '87: Proceedings of the 14th annual international symposium on Computer architecture

June 1987

321 pages

ISBN:0818607769

DOI:10.1145/30350

Editor:
D. St. Clair

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1987

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ISCA87: The 14th Annual International Symposium on Computer Architecture

June 2 - 5, 1987

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Chen H(2011)Low-power way-predicting cache based on intrablock accessJournal of the Chinese Institute of Engineers10.1080/02533839.2011.57650034:4(529-537)Online publication date: Jun-2011
https://doi.org/10.1080/02533839.2011.576500
Kannan MDeepu KIype JParthasarathy RGautham P(2010)Power Consumption Analysis of Direct, Set Associative and Phased Set Associative Cache Organizations in Alpha AXP 21064 ProcessorInformation Processing and Management10.1007/978-3-642-12214-9_20(114-119)Online publication date: 2010
https://doi.org/10.1007/978-3-642-12214-9_20
Megalingam RDeepu KJoseph IVikram V(2009)Phased set associative cache design for reduced power consumption2009 2nd IEEE International Conference on Computer Science and Information Technology10.1109/ICCSIT.2009.5234663(551-556)Online publication date: Aug-2009
https://doi.org/10.1109/ICCSIT.2009.5234663
Kaxiras SMartonosi M(2008)Computer Architecture Techniques for Power-EfficiencySynthesis Lectures on Computer Architecture10.2200/S00119ED1V01Y200805CAC0043:1(1-207)Online publication date: Jan-2008
https://doi.org/10.2200/S00119ED1V01Y200805CAC004
Naz AKavi KRezaei MLi WBartolini SFoglia PGiorgi RPrete C(2005)Making a case for split data caches for embedded applicationsProceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture10.1145/1152779.1147355(19-26)Online publication date: 17-Sep-2005
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Naz AKavi KRezaei MLi W(2005)Making a case for split data caches for embedded applicationsACM SIGARCH Computer Architecture News10.1145/1147349.114735534:1(19-26)Online publication date: 17-Sep-2005
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Min RJone WHu YJoshi RChoi KTiwari VRoy K(2004)Location cacheProceedings of the 2004 international symposium on Low power electronics and design10.1145/1013235.1013271(120-125)Online publication date: 9-Aug-2004
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Min RZhiyong Xu Yiming Hu Jone W(2004)Partial tag comparison: a new technology for power-efficient set-associative cache designs17th International Conference on VLSI Design. Proceedings.10.1109/ICVD.2004.1260922(183-188)Online publication date: 2004
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Hu ZKaxiras SMartonosi M(2004)Improving Power Efficiency with an Asymmetric Set-Associative CacheHigh Performance Memory Systems10.1007/978-1-4419-8987-1_6(79-96)Online publication date: 2004
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Huang MRenau JYoo STorrellas JMacii EDe VIrwin M(2001)L1 data cache decomposition for energy efficiencyProceedings of the 2001 international symposium on Low power electronics and design10.1145/383082.383086(10-15)Online publication date: 6-Aug-2001
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Location cache: a low-power L2 cache system

Application-adaptive intelligent cache memory system

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Location cache: a low-power L2 cache system

Application-adaptive intelligent cache memory system

An intelligent cache system with hardware prefetching for high performance

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