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Improved Reliability of FPGA-Based PUF Identification Generator Design

Published: 27 May 2017 Publication History

Abstract

Physical unclonable functions (PUFs), a form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n-bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs and can consume excessive resources. To address these problems, in this article we present an efficient, lightweight, and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed that improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed post-characterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25°C to 70°C with ± 10% variation in the supply voltage.

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems  Volume 10, Issue 3
September 2017
187 pages
ISSN:1936-7406
EISSN:1936-7414
DOI:10.1145/3102109
  • Editor:
  • Steve Wilton
Issue’s Table of Contents
This work is licensed under a Creative Commons Attribution International 4.0 License.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 May 2017
Accepted: 01 January 2017
Revised: 01 December 2016
Received: 01 June 2016
Published in TRETS Volume 10, Issue 3

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Author Tags

  1. Physical unclonable functions (PUFs)
  2. authentication
  3. field programmable gate arrays (FPGAs)
  4. identification generation
  5. reliability

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  • (2024)Machine Learning Attacks on Challenge-Response Obfuscations in Strong PUFs2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HOST55342.2024.10545395(361-372)Online publication date: 6-May-2024
  • (2024)Vulnerabilities and Challenges in the Development of PUF-Based Authentication Protocols on FPGAs: A Brief Review2024 IEEE Conference on Dependable and Secure Computing (DSC)10.1109/DSC63325.2024.00021(58-65)Online publication date: 6-Nov-2024
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  • (2023)Exploiting the DD-Cell as an Ultra-Compact Entropy Source for an FPGA-Based Re-Configurable PUF-TRNG ArchitectureIEEE Access10.1109/ACCESS.2023.330490111(86178-86195)Online publication date: 2023
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