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Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption

Published: 10 May 2017 Publication History

Abstract

The logic-in-memory architecture is highly promising for high-throughput data-driven applications. This paper presents a novel dual-mode magnetic crossbar architecture consisting of perpendicularly cross-coupled magnetic racetrack nanowires, which could morph between non-volatile multi-bit racetrack memory mode and in-memory data encryption mode. The proposed magnetic crossbar is able to automatically perform parallel in-memory bit-wise XOR computations of the data stored in the racetrack memories with the help of magnetic coupling physics without complex peripheral circuits, which could be leveraged to design energy efficient in-memory data encryption engine. We employ Advanced Encryption Standard (AES) algorithm to elucidate the efficiency of the proposed design. The device-to-architecture level simulation results show that the proposed architecture can achieve 70% and 17.5% lower energy consumption compared to CMOS-ASIC and recent domain wall (DW) AES implementations, respectively. In addition, the AES encryption speed increases by 29.7% compared to the DW-AES implementation.

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  • (2018)IMFlexComACM Journal on Emerging Technologies in Computing Systems10.1145/322304714:3(1-18)Online publication date: 23-Oct-2018
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cover image ACM Conferences
GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017
May 2017
516 pages
ISBN:9781450349727
DOI:10.1145/3060403
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 10 May 2017

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Author Tags

  1. in-memory encryption
  2. magnetic coupling
  3. magnetic crossbar

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  • Research-article

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GLSVLSI '17
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GLSVLSI '17: Great Lakes Symposium on VLSI 2017
May 10 - 12, 2017
Alberta, Banff, Canada

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GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;
Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2023)Aligner-D: Leveraging In-DRAM Computing to Accelerate DNA Short Read AlignmentIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324154513:1(332-343)Online publication date: Mar-2023
  • (2022)pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup TablesProceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO56248.2022.00067(900-919)Online publication date: 1-Oct-2022
  • (2018)IMFlexComACM Journal on Emerging Technologies in Computing Systems10.1145/322304714:3(1-18)Online publication date: 23-Oct-2018
  • (2018)Exploring a SOT-MRAM Based In-Memory Computing for Data ProcessingIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2018.28369674:4(676-685)Online publication date: 1-Oct-2018
  • (2018)IMCS2: Novel Device-to-Architecture Co-Design for Low-Power In-Memory Computing Platform Using Coterminous Spin SwitchIEEE Transactions on Magnetics10.1109/TMAG.2018.281995954:7(1-14)Online publication date: Jul-2018
  • (2018)Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00103(533-538)Online publication date: Jul-2018
  • (2017)Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8053122(1109-1112)Online publication date: Aug-2017
  • (2017)In-Memory Computing with Spintronic Devices2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.116(683-688)Online publication date: Jul-2017
  • (2017)Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction2017 IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2017.78(439-446)Online publication date: Nov-2017

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