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Comparative Analysis of Hardware Obfuscation for IP Protection

Authors:

Mark Tehranipoor,

Swarup BhuniaAuthors Info & Claims

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

Pages 363 - 368

https://doi.org/10.1145/3060403.3060495

Published: 10 May 2017 Publication History

Abstract

In the era of globalized Integrated Circuit (IC) design and manufacturing flow, a rising issue to the silicon industry is various attacks on hardware intellectual property (IP). As a measure to ensure security along the supply chain against IP piracy, tampering and reverse engineering, hardware obfuscation is considered a reliable defense mechanism. Sequential and combinational obfuscations are the primary classes of obfuscation, and multiple methods have been proposed in each type in recent years. This paper presents an overview of obfuscation techniques and a qualitative comparison of the two major types.

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Cited By

Dharsee KCriswell JCalandrino JTroncoso C(2023)JinnProceedings of the 32nd USENIX Conference on Security Symposium10.5555/3620237.3620627(6965-6982)Online publication date: 9-Aug-2023
https://dl.acm.org/doi/10.5555/3620237.3620627
Mirmohammadi ZEtemadi Borujeni S(2023)A New Optimal Method for the Secure Design of Combinational Circuits against Hardware Trojans Using Interference Logic LockingElectronics10.3390/electronics1205110712:5(1107)Online publication date: 23-Feb-2023
https://doi.org/10.3390/electronics12051107
Aksoy LNguyen QAlmeida FRaik JFlottes MDupuis SPagliarini S(2023)Hybrid Protection of Digital FIR FiltersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.325364131:6(812-825)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3253641
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Index Terms

Comparative Analysis of Hardware Obfuscation for IP Protection
1. Security and privacy
  1. Security in hardware
    1. Hardware security implementation
      1. Hardware-based security protocols

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cover image ACM Conferences

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

May 2017

516 pages

ISBN:9781450349727

DOI:10.1145/3060403

General Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada
,
Program Chairs:
Miroslav N. Velev
Aries Design Automation, USA
,
Deming Chen
University of Illinois, USA

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 May 2017

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GLSVLSI '17: Great Lakes Symposium on VLSI 2017

May 10 - 12, 2017

Alberta, Banff, Canada

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GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Dharsee KCriswell JCalandrino JTroncoso C(2023)JinnProceedings of the 32nd USENIX Conference on Security Symposium10.5555/3620237.3620627(6965-6982)Online publication date: 9-Aug-2023
https://dl.acm.org/doi/10.5555/3620237.3620627
Mirmohammadi ZEtemadi Borujeni S(2023)A New Optimal Method for the Secure Design of Combinational Circuits against Hardware Trojans Using Interference Logic LockingElectronics10.3390/electronics1205110712:5(1107)Online publication date: 23-Feb-2023
https://doi.org/10.3390/electronics12051107
Aksoy LNguyen QAlmeida FRaik JFlottes MDupuis SPagliarini S(2023)Hybrid Protection of Digital FIR FiltersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.325364131:6(812-825)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3253641
Sisejkovic DCollini LTan BPilato CKarri RLeupers ROshana R(2022)Designing ML-resilient locking at register-transfer levelProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530541(769-774)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530541
Nasir NAli Malik ATahir IMasood ARiaz N(2022)Ephemeral Key-based Hybrid Hardware Obfuscation2022 19th International Bhurban Conference on Applied Sciences and Technology (IBCAST)10.1109/IBCAST54850.2022.9990230(646-652)Online publication date: 16-Aug-2022
https://doi.org/10.1109/IBCAST54850.2022.9990230
Rai SGarg SPilato CHerdt VMoussavi ESisejkovic DKarri RDrechsler RMerchant FKumar A(2021)Vertical IP Protection of the Next-Generation Devices: Quo Vadis?2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474132(1905-1914)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474132
Sisejkovic DMerchant FReimann LSrivastava HHallawa ALeupers R(2021)Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary ApproachACM Journal on Emerging Technologies in Computing Systems10.1145/343138917:3(1-26)Online publication date: 11-May-2021
https://dl.acm.org/doi/10.1145/3431389
Kalayappan RSarangi S(2021)A Formal Approach to Accountability in Heterogeneous Systems-on-ChipIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2020.297041718:6(2926-2940)Online publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1109/TDSC.2020.2970417
Šišejković DMerchant FReimann LLeupers RGiacometti MKegreiß SCorporaal H(2020)A secure hardware-software solution based on RISC-V, logic locking and microkernelProceedings of the 23th International Workshop on Software and Compilers for Embedded Systems10.1145/3378678.3391886(62-65)Online publication date: 25-May-2020
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Šišejković DMerchant FLeupers RAscheid GKegreiss SHomayoun HTaskin BMohsenin TZhao W(2019)Control-LockProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317983(27-32)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3317983
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