research-article

Exploiting Non-Volatility for Information Processing

Authors:

Robert Perricone,

Michael Niemier,

X. Sharon HuAuthors Info & Claims

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

Pages 305 - 310

https://doi.org/10.1145/3060403.3066872

Published: 10 May 2017 Publication History

Abstract

The emergence of non-volatile (NV) technologies provides an opportunity to overcome limitations of CMOS (e.g., the growth of leakage power), while simultaneously providing a degree of non-volatility to the processor. Spintronic NV technologies are of particular interest due to their high integration density, low device count, radiation hardness, and non-volatility when compared to CMOS. Quantifying the impact of spintronic NV technologies at the architecture/application levels introduces a unique challenge as the granularity of technology integration can vary significantly (i.e., from heterogeneous architectures with NV cache/memory and CMOS-based logic, to completely NV architectures). In this work, we explore three classes of NV processors (NVPs) and define metrics for quantifying their respective energy savings. As case studies, we evaluate the impact of NV technologies for both an energy harvesting non-pipelined processor and a general purpose processor executing scientific applications under varying degrees of parallelism.

References

[1]

International technology roadmap for semiconductors, 2011 report. 309

[2]

B. Behin-Aein, D. Datta, S. Salahuddin, and S. Datta. Proposal for an all-spin logic device with built-in memory. Nature nanotechnology, 5(4):266--270, 2010.

[3]

S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S. H. Lee, and K. Skadron. Rodinia: A benchmark suite for heterogeneous computing. In IEEE International Symposium on Workload Characterization, pages 44--54, Oct 2009.

Digital Library

[4]

S. Fukami, T. Suzuki, N. Ohshima, K. Nagahara, and N. Ishiwata. Micromagnetic analysis of current driven domain wall motion in nanostrips with perpendicular magnetic anisotropy. Journal of Applied Physics, 103(7):07E718, 2008.

[5]

X. Guo, E. Ipek, and T. Soyata. Resistive computation: Avoiding the power wall with low-leakage, stt-mram based computing. In International Symposium on Computer Architecture, pages 371--382. ACM, 2010.

Digital Library

[6]

S. Kannan, A. Gavrilovska, K. Schwan, and D. Milojicic. Optimizing checkpoints using nvm as virtual memory. In International Symposium on Parallel and Distributed Processing, pages 29--40, May 2013.

Digital Library

[7]

J. Kim, A. Paul, P. A. Crowell, S. J. Koester, S. S. Sapatnekar, J. P. Wang, and C. H. Kim. Spin-based computing: Device concepts, current status, and a case study on a high-performance microprocessor. Proceedings of the IEEE, 103(1):106--130, Jan 2015.

[8]

L. Liu, O. J. Lee, T. J. Gudmundsen, D. C. Ralph, and R. A. Buhrman. Current-induced switching of perpendicularly magnetized magnetic layers using spin torque from the spin hall effect. Phys. Rev. Lett., 109:096602, Aug 2012.

[9]

L. Liu, C.-F. Pai, Y. Li, H. Tseng, D. Ralph, and R. Buhrman. Spin-torque switching with the giant spin hall effect of tantalum. Science, 336(6081):555--558, 2012.

[10]

L. Liu, C.-F. Pai, Y. Li, H. W. Tseng, D. C. Ralph, and R. A. Buhrman. Spin-torque switching with the giant spin hall effect of tantalum. Science, 336(6081):555--558, 2012.

[11]

Y. Liu, Z. Wang, A. Lee, F. Su, C. P. Lo, Z. Yuan, C. C. Lin, Q. Wei, Y. Wang, Y. C. King, C. J. Lin, P. Khalili, K. L. Wang, M. F. Chang, and H. Yang. A 65nm reram-enabled nonvolatile processor with 6x reduction in restore time and 4x higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. In IEEE International Solid-State Circuits Conference, pages 84--86, Jan 2016.

[12]

K. Ma, Y. Zheng, S. Li, K. Swaminathan, X. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan. Architecture exploration for ambient energy harvesting nonvolatile processors. In International Symposium on High Performance Computer Architecture, pages 526--537, Feb 2015.

[13]

S. Manipatruni, D. E. Nikonov, and I. A. Young. Energy-delay performance of giant spin hall effect switching for dense magnetic memory. Applied Physics Express, 7(10):103001, 2014.

[14]

M. G. Mankalale, Z. Liang, A. K. Smith, D. C. Mahendra, J. Wang, and S. S. Sapatnekar. A fast magnetoelectric device based on current--driven domain wall propagation. In IEEE Device Research Conference, June 2016.

[15]

M. G. Mankalale, Z. Liang, Z. Zhao, C. H. Kim, J. Wang, and S. S. Sapatnekar. CoMET: Composite input magnetoelectric based logic technology. 2016. https://arxiv.org/abs/1611.09714.

[16]

D. Nikonov and I. Young. Benchmarking of beyond-cmos exploratory devices for logic integrated circuits. IEEE J. on Exploratory Solid-State Computational Devices and Circuits, 1:3--11, Dec. 2015.

[17]

T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh. A 1 mb nonvolatile embedded memory using 4t2mtj cell with 32 b fine-grained power gating scheme. IEEE Journal of Solid-State Circuits, 48(6):1511--1520, 2013.

[18]

R. Perricone, I. Ahmed, Z. Liang, M. Mankalale, X. S. Hu, C. Kim, M. Niemier, S. Sapatnekar, and J. Wang. Advanced spintronic memory and logic for non-volatile processors. In Design, Automation Test in Europe Conference Exhibition, March 2017.

[19]

R. Perricone, X. S. Hu, J. Nahas, and M. Niemier. Can beyond-cmos devices illuminate dark silicon? In Design, Automation Test in Europe Conference Exhibition, pages 13--18, March 2016.

Digital Library

[20]

N. Sakimura, Y. Tsuji, R. Nebashi, H. Honjo, A. Morioka, K. Ishihara, K. Kinoshita, S. Fukami, S. Miura, N. Kasai, T. Endoh, H. Ohno, T. Hanyu, and T. Sugibayashi. A 90nm 20mhz fully nonvolatile microcontroller for standby-power-critical applications. In IEEE International Solid-State Circuits Conference, pages 184--185, Feb 2014.

[21]

R. Takemura, T. Kawahara, K. Miura, H. Yamamoto, J. Hayakawa, N. Matsuzaki, K. Ono, M. Yamanouchi, K. Ito, H. Takahashi, S. Ikeda, H. Hasegawa, H. Matsuoka, and H. Ohno. A 32-mb spram with 2t1r memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme. IEEE J. of Solid-State Cir., 45(4):869--879, 2010.

[22]

Y. Wang, Y. Liu, S. Li, D. Zhang, B. Zhao, M. F. Chiang, Y. Yan, B. Sai, and H. Yang. A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. In ESSCIRC, pages 149--152, Sept 2012.

[23]

Z. Zhao, M. Jamali, A. K. Smith, and J.-P. Wang. Spin hall switching of the magnetization in ta/tbfeco structures with bulk perpendicular anisotropy. Applied Physics Letters, 106(13):132404, 2015.

Cited By

Chen XSun XWang PDatta SHu XYin XJerry MYu SLaguna ANi KNiemier MReis D(2020)The Impact of Ferroelectric FETs on Digital and Analog Circuits and ArchitecturesIEEE Design & Test10.1109/MDAT.2019.294409437:1(79-99)Online publication date: Feb-2020
https://doi.org/10.1109/MDAT.2019.2944094
Perricone RLiang ZMankalale MNiemier MSapatnekar SWang JHu X(2019)An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714916(390-395)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8714916

Index Terms

Exploiting Non-Volatility for Information Processing
1. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
      1. Emerging architectures
    2. Spintronics and magnetic technologies
  2. Power and energy
    1. Power estimation and optimization

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Published In

cover image ACM Conferences

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

May 2017

516 pages

ISBN:9781450349727

DOI:10.1145/3060403

General Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada
,
Program Chairs:
Miroslav N. Velev
Aries Design Automation, USA
,
Deming Chen
University of Illinois, USA

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE CEDA
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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 May 2017

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Microelectronics Advanced Research Corporation

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GLSVLSI '17

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SIGDA

GLSVLSI '17: Great Lakes Symposium on VLSI 2017

May 10 - 12, 2017

Alberta, Banff, Canada

Acceptance Rates

GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Chen XSun XWang PDatta SHu XYin XJerry MYu SLaguna ANi KNiemier MReis D(2020)The Impact of Ferroelectric FETs on Digital and Analog Circuits and ArchitecturesIEEE Design & Test10.1109/MDAT.2019.294409437:1(79-99)Online publication date: Feb-2020
https://doi.org/10.1109/MDAT.2019.2944094
Perricone RLiang ZMankalale MNiemier MSapatnekar SWang JHu X(2019)An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714916(390-395)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8714916

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