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Path delay fault testing of ICs with embedded intellectual property blocks

Authors:

D. Nikolos,

Th. Haniotakis,

H. T. Vergos,

Y. TsiatouhasAuthors Info & Claims

DATE '99: Proceedings of the conference on Design, automation and test in Europe

Pages 27 - es

https://doi.org/10.1145/307418.307468

Published: 01 January 1999 Publication History

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Haniotakis TKalligeros ENikolos DSidiropulos GTsiatouhas YVergos H(2000)A class of easily path delay fault testable circuits2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)10.1109/SSMSD.2000.836466(165-170)Online publication date: 2000
https://doi.org/10.1109/SSMSD.2000.836466
Kim HHayes J(1999)Delay Fault Testing of IP-Based Designs Via Symbolic Path ModelingProceedings of the 1999 IEEE International Test Conference10.5555/518925.939468Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939468
Sidiropoulos GVergos HNikolos D(1999)Easily path delay fault testable non-restoring cellular array dividersProceedings Eighth Asian Test Symposium (ATS'99)10.1109/ATS.1999.810728(47-52)Online publication date: 1999
https://doi.org/10.1109/ATS.1999.810728

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Path delay fault testing of ICs with embedded intellectual property blocks
1. Hardware

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DATE '99: Proceedings of the conference on Design, automation and test in Europe

January 1999

730 pages

ISBN:1581131216

DOI:10.1145/307418

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Haniotakis TKalligeros ENikolos DSidiropulos GTsiatouhas YVergos H(2000)A class of easily path delay fault testable circuits2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)10.1109/SSMSD.2000.836466(165-170)Online publication date: 2000
https://doi.org/10.1109/SSMSD.2000.836466
Kim HHayes J(1999)Delay Fault Testing of IP-Based Designs Via Symbolic Path ModelingProceedings of the 1999 IEEE International Test Conference10.5555/518925.939468Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939468
Sidiropoulos GVergos HNikolos D(1999)Easily path delay fault testable non-restoring cellular array dividersProceedings Eighth Asian Test Symposium (ATS'99)10.1109/ATS.1999.810728(47-52)Online publication date: 1999
https://doi.org/10.1109/ATS.1999.810728

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Path Delay Testing: Variable-Clock Versus Rated-Clock

Design-specific path delay testing in lookup-table-based FPGAs

Transition path delay faults: a new path delay fault model for small and large delay defects

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Path Delay Testing: Variable-Clock Versus Rated-Clock

Design-specific path delay testing in lookup-table-based FPGAs

Transition path delay faults: a new path delay fault model for small and large delay defects

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